Page 1 MF1072-04 Dot Matrix Graphics LCD Controller S1D13504 Series Technical Manual...
Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products.
Page 3: Evaluation Board
The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.
Page 4: Hardware Functional Specification
S1D13504 Series Technical Manual HARDWARE FUNCTIONAL SPECIFICATION PROGRAMMING NOTES AND EXAMPLES UTILITIES S5U13504P00C ISA BUS EVALUATION BOARD USER’S MANUAL APPLICATION NOTES...
Page 6: Table Of Contents
7.2 Clock Input Requirements ......................1-30 7.3 Memory Interface Timing......................1-31 EDO-DRAM Read Timing ......................1-31 EDO-DRAM Write Timing ......................1-32 EDO-DRAM Read-Write Timing....................1-33 EDO-DRAM CAS Before RAS Refresh Timing................1-34 EDO-DRAM Self-Refresh Timing.....................1-34 FPM-DRAM Read Timing ......................1-35 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 7 4 Bit-Per-Pixel Color Mode ....................1-97 8 Bit-Per-Pixel Color Mode ....................1-98 13 P ......................1-99 OWER ODES 13.1 Hardware Suspend ........................1-99 13.2 Software Suspend........................1-99 13.3 Power Save Mode Function Summary..................1-100 EPSON 1-ii S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 8 CONTENTS 13.4 Pin States in Power Save Modes ....................1-100 14 M ......................1-101 ECHANICAL 14.1 QFP15-128pin (S1D13504F00A) ....................1-101 14.2 TQFP15-128pin (S1D13504F01A) ....................1-102 14.3 QFP20-144pin (S1D13504F02A) ....................1-103 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-iii SPECIFICATION (X19A-A-002-17)
Page 9 Dual Monochrome 8-Bit Panel A.C. Timing ............... 1-54 Figure 7-38 Dual Color 8-Bit Panel Timing.................... 1-55 Figure 7-39 Dual Color 8-Bit Panel A.C. Timing..................1-56 Figure 7-40 Dual Color 16-Bit Panel Timing..................1-57 EPSON 1-iv S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 10 Figure 14-2 Mechanical Drawing TQFP15-128pin ................1-102 Figure 14-3 Mechanical Drawing QFP20-144pin.................1-103 List of Tables Table 2-1 S1D13504 Series Package List....................1-3 Table 5-1 Host Interface Pin Descriptions ..................1-10 Table 5-2 Memory Interface Pin Descriptions ..................1-12 Table 5-3 LCD Interface Pin Descriptions ..................1-13 Table 5-4 Clock Input Pin Description ....................1-13...
Page 11 Table 11-3 Example Frame Rates ....................... 1-92 Table 12-1 Look-Up Table Configurations ................... 1-94 Table 13-1 Power Save Mode Function Summary ................1-100 Table 13-2 Pin States in Power Save Modes..................1-100 EPSON 1-vi S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 12: Introduction
RAMDAC interface allowing simultaneous display of both the CRT and LCD panel. A 16-bit memory interface supports up to 2M bytes of FPM-DRAM or EDO-DRAM. Flexi- ble operating voltages from 2.7V to 5.5V provide for very low power consumption. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 13: Features
- Line-Doubling mode for simultaneous display of 240-line images on 240-line LCD and 480- line CRT. - Even-Scan and interlace modes for simultaneous display of 480-line images on 240-line LCD and 480-line CRT. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 14: Display Modes
• The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose Output that can be used to control the LCD backlight – its power-on polarity is selected by an MD conﬁguration pin. 2.7 Package and Pin Table 2-1 S1D13504 Series Package List Name Package S1D13504F00A...
Page 15: Typical System Implementation Diagrams
AB0# FPFRAME FPFRAME Display UDS# WE1# FPLINE FPLINE DRDY R/W# RD/WR# DTACK# WAIT# LCDPWR BCLK BUSCLK RESET# RESET# 1Mx16 FPM/EDO-DRAM Figure 3-2 Typical System Diagram – MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000) EPSON S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 16: Figure 3-3 Typical System Diagram - Mc68K Bus 2, 256Kx16 Fpm/Edo-Dram (32-Bit Mc68030)
S1D13504 WE0# WE0# FPFRAME FPFRAME Display WE1# WE1# FPLINE FPLINE RD0# DRDY RD1# RD/WR# WAIT# WAIT# LCDPWR BCLK BUSCLK RESET# RESET# 1Mx16 FPM/EDO-DRAM Figure 3-4 Typical System Diagram – Generic Bus, 1Mx16 FPM/EDO-DRAM EPSON S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 17: Block Description
The LCD Interface block performs frame rate modulation for passive LCD panels. It also generates the correct data format and timing control signals for various LCD and TFT panels. 4.2.6 Power Save The Power Save block contains the power save mode circuitry. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 18: Pin Out
TESTEN BUSCLK AB20 LCAS# AB19 UCAS# S1D13504F00A AB18 AB17 RAS# AB16 AB15 AB14 MA11 AB13 AB12 MA10 AB11 AB10 COREV Figure 5-1 Pinout Diagram of S1D13504F00A Package type: 128 pin surface mount QFP15 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 19: Pinout Diagram For S1D13504F01A
TESTEN BUSCLK AB20 LCAS# AB19 UCAS# S1D13504F01A AB18 AB17 RAS# AB16 AB15 AB14 MA11 AB13 AB12 MA10 AB11 AB10 COREV Figure 5-2 Pinout Diagram of S1D13504F01A Package type: 128 pin surface mount TQFP15 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 20: Pinout Diagram For S1D13504F02A
TESTEN BUSCLK AB20 LCAS# AB19 UCAS# S1D13504F02A AB18 AB17 RAS# AB16 AB15 AB14 MA11 AB13 AB12 MA10 AB11 AB10 COREV Figure 5-3 Pinout Diagram of S1D13504F02A Package type: 144 pin surface mount QFP20 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 21: Pin Description
Mapping” on page 64. See Table 5-9, “Host Bus Interface Pin Mapping,” on page 16. Hi-Z Chip select input. See Table 5-9, “Host Bus Interface Pin Map- ping,” on page 16. EPSON 1-10 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 22 See Table 5-9, “Host Bus Interface Pin Mapping,” on page 16. RESET# Input 0 Active low input to clear all internal registers and to force all sig- nals to their inactive states. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-11 SPECIFICATION (X19A-A-002-17)
Page 23: Memory Interface
• For symmetrical 2M byte DRAM and all 512K byte DRAM, this pin can be used as general purpose IO (GPIO2). See Table 5-10, “Memory Interface Pin Mapping,” on page 16 for summary. *1: When conﬁgured as IO pins. EPSON 1-12 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 24: Lcd Interface
This pin has multiple functions. Output 0 • Register Select bit 1 for external RAMDAC support. (∗1) • General Purpose IO (GPIO9). See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,” on page 17. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-13 SPECIFICATION (X19A-A-002-17)
Page 25: Miscellaneous
Test Enable. This in should be connected to V for normal oper- (pulled 0) ation. – – 1, 2 – – No connect 35–38 71–74 107–110 143, 144 ∗1: When conﬁgured as IO pin. Output may be 1 or 0. EPSON 1-14 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 26: Power Supply
39, 111 Core V 14, 46, 83, 110 16, 52, 93, 124 IO V 15, 32, 51, 68 17, 34, 57, 78 Common V 74, 87, 96 104 84, 97, 106 118, 123 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-15 SPECIFICATION (X19A-A-002-17)
Page 27: Summary Of Configuration Options
LCAS# CAS# LWE# LWE# LWE# LWE# RAS# RAS# *1: All GPIO pins default to input on reset, and unless programmed otherwise should be connected to either or IO V if not used. EPSON 1-16 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 28: Table 5-11 Lcd, Crt, Ramdac Interface Pin Mapping
*2: If no LCD is active these pins are driven low. *3: All GPIO pins default to input on reset, and unless programmed otherwise should be connected to either or IO V if not used. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-17 SPECIFICATION (X19A-A-002-17)
Page 29: C. Characteristics
Type 1 - TS1, CO1, TS1D = -1.5mA -0.4 Type 2 - TS2, CO2 = -3mA Type 3 - TS3, CO3 = -6mA = Max.. Output Leakage Current µA Output Pin Capacitance Bidirectional Pin Capacitance EPSON 1-18 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 30: C. Characteristics
≤ 5 nsec (10% to 90%) and T rise fall = 50pF (Bus / MPU Interface) = 100pF (LCD Panel Interface) = 10pF (Display Buffer Interface) C = 10pF (CRT / DAC Interface) EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-19 SPECIFICATION (X19A-A-002-17)
Page 31: Cpu Interface Timing
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later. EPSON 1-20 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 32: Figure 7-2 Sh-3 Write Bus Timing
Note: 1. If the S1D13504 host interface is disabled, the timing for WAIT# driven is relative to the falling edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-21 SPECIFICATION (X19A-A-002-17)
Page 33: Mc68K Bus 1 Interface Timing (E.g. Mc68000)
Note: 1. If the S1D13504 host interface is disabled, the timing for DTACK# driven high is relative to the fall- ing edge of AS# or the first positive edge of CLK after A[20:1], M/R# becomes valid, whichever one is later. EPSON 1-22 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 34: Figure 7-4 Mc68000 Read Bus Timing
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of UDS#/LDS# or the first positive edge of CLK after A[20:1], M/R# becomes valid, whichev- er one is later. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-23 SPECIFICATION (X19A-A-002-17)
Page 35: Mc68K Bus 2 Interface Timing (E.g. Mc68030)
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# becomes valid, whichever occurs later. EPSON 1-24 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 36: Figure 7-6 Mc68030 Read Bus Timing
Note: 1 .If the S1D13504 host interface is disabled, the timing for DSACK1# driven high is relative to the falling edge of AS# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-25 SPECIFICATION (X19A-A-002-17)
Page 37: Generic Mpu Interface Synchronous Timing
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0], M/R# becomes valid, which- ever one is later. EPSON 1-26 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 38: Figure 7-8 Generic Write Bus Synchronous Timing
Note: 1. If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# and WE0#, WE1# or the first positive edge of BCLK after A[20:0], M/R# becomes val- id, whichever one is later. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-27 SPECIFICATION (X19A-A-002-17)
Page 39: Generic Mpu Interface Asynchronous Timing
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0], M/R# becomes valid, which- ever one is later. EPSON 1-28 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 40: Figure 7-10 Generic Write Bus Asynchronous Timing
Note: 1. If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# or the first positive edge of BCLK after A[20:0], M/R# becomes valid, whichever one is later. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-29 SPECIFICATION (X19A-A-002-17)
Page 41: Clock Input Requirements
Input Clock Pulse Width High (CLKI) CLKI Input Clock Pulse Width Low (CLKI) CLKI Note: When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2). EPSON 1-30 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 42: Memory Interface Timing
Access time from RAS# (REG[22h] bits [3:2] = 01) 2.45 - 12 Access time from CAS# - 10 Access time from CAS# precharge, column address 1.45 Read Data hold after CAS# low Read Data turn-off delay from RAS# EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-31 SPECIFICATION (X19A-A-002-17)
Page 43: Edo-Dram Write Timing
RAS# to CAS# delay time (REG[22h] bits [3:2] = 01) 1.45 1.55 Write command setup time 0.45 Write command hold time 0.45 Write Data setup time 0.45 Write Data hold time 0.45 EPSON 1-32 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 44: Edo-Dram Read-Write Timing
RAS# to CAS# delay time (REG[22h] bits [3:2] = 01) 1.45 1.55 Read Data turn-off delay from WE# Write Data delay from WE# (REG[22h] bit 7 = 0) 1.45 Write Data delay from WE# (REG[22h] bit 7 = 1) 0.45 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-33 SPECIFICATION (X19A-A-002-17)
Page 45: Edo-Dram Cas Before Ras Refresh Timing
CAS# setup time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 00) RAS# precharge time (REG[22h] bits [3:2] = 01) 1.45 RAS# precharge time (REG[22h] bits [3:2] = 10) EPSON 1-34 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 46: Fpm-Dram Read Timing
Access time from RAS# (REG[22h] bit 4 = 0 and bits [3:2] = 01) 2.45 Access time from CAS# 0.45 Access time from CAS# precharge Read Data hold from CAS# or RAS# EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-35 SPECIFICATION (X19A-A-002-17)
Page 47: Fpm-Dram Write Timing
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 01) Write command setup time 0.45 Write command hold time 0.45 Write Data setup time 0.45 Write Data hold time 0.45 EPSON 1-36 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 48: Fpm-Dram Read-Write Timing
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 01) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 01) Read Data turn-off delay from CAS# Write Data enable delay from WE# 0.45 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-37 SPECIFICATION (X19A-A-002-17)
Page 49: Fpm-Dram Cas# Before Ras# Refresh Timing
CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# setup time (CAS# before RAS# refresh) 0.45 RAS# precharge time (REG[22h] bits [3:2] = 00) 2.45 RAS# precharge time (REG[22h] bits [3:2] = 01 or 10) 1.45 EPSON 1-38 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 50: Display Interface
PCLK FPLINE, FPSHIFT, FPDAT[15:0], DRDY active to LCDPWR, on and Frames FPFRAME active Note: Where T is the period of FPFRAME and T is the period of the pixel clock. FPFRAME PCLK EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-39 SPECIFICATION (X19A-A-002-17)
Page 51: Suspend Timing
Note: 1. t , and t are measured from the first CLKI after SUSPEND# inactive. 2. CLKI may be active throughout SUSPEND# active. 3. Where MCLK is the period of the memory clock. EPSON 1-40 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 52: Single Monochrome 4-Bit Panel Timing
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)∗8Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-41 SPECIFICATION (X19A-A-002-17)
Page 53: Figure 7-25 Single Monochrome 4-Bit Panel A.c. Timing
= [((REG[04h] bits [6:0]) + 1)∗8 - 1] Ts 5min 5. t = [((REG[05h] bits [4:0]) + 1)∗8 - 25] Ts 6min 6. t = [((REG[05h] bits [4:0]) + 1)∗8 - 16] Ts 9min EPSON 1-42 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 54: Single Monochrome 8-Bit Panel Timing
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)∗8Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-43 SPECIFICATION (X19A-A-002-17)
Page 55: Figure 7-27 Single Monochrome 8-Bit Panel A.c. Timing
= [((REG[04h] bits [6:0]) + 1)∗8 - 1] Ts 5min 5. t = [((REG[05h] bits [4:0]) + 1)∗8 - 23] Ts 6min 6. t = [((REG[05h] bits [4:0]) + 1)∗8 - 14] Ts 9min EPSON 1-44 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 56: Single Color 4-Bit Panel Timing
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)∗8Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-45 SPECIFICATION (X19A-A-002-17)
Page 57: Figure 7-29 Single Color 4-Bit Panel A.c. Timing
= [((REG[04h] bits [6:0]) + 1)∗8 - 1] Ts 5min 5. t = [((REG[05h] bits [4:0]) + 1)∗8 - 26] Ts 6min 6. t = [((REG[05h] bits [4:0]) + 1)∗8 - 17] Ts 9min EPSON 1-46 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 58: Single Color 8-Bit Panel Timing (Format 1)
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)∗8Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-47 SPECIFICATION (X19A-A-002-17)
Page 59: Figure 7-31 Single Color 8-Bit Panel A.c. Timing (Format 1)
= [((REG[05h] bits [4:0]) + 1)∗8 - 27] Ts 5min 6. t = [((REG[05h] bits [4:0]) + 1)∗8 - 18] Ts 8min 7. t = [((REG[05h] bits [4:0]) + 1)∗8 - 18]+T11 Ts 8min EPSON 1-48 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 60: Single Color 8-Bit Panel Timing (Format 2)
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)∗8Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-49 SPECIFICATION (X19A-A-002-17)
Page 61: Figure 7-33 Single Color 8-Bit Panel A.c. Timing (Format 2)
= [((REG[04h] bits [6:0]) + 1)∗8 - 1] Ts 5min 5. t = [((REG[05h] bits [4:0]) + 1)∗8 - 26] Ts 6min 6. t = [((REG[05h] bits [4:0]) + 1)∗8 - 17] Ts 7min EPSON 1-50 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 62: Single Color 16-Bit Panel Timing
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)∗8Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-51 SPECIFICATION (X19A-A-002-17)
Page 63: Figure 7-35 Single Color 16-Bit Panel A.c. Timing
= [((REG[04h] bits [6:0]) + 1)∗8 - 1] Ts 5min 5. t = [((REG[05h] bits [4:0]) + 1)∗8 - 25] Ts 6min 6. t = [((REG[05h] bits [4:0]) + 1)∗8 - 16] Ts 7min EPSON 1-52 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 64: Dual Monochrome 8-Bit Panel Timing
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)∗8Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-53 SPECIFICATION (X19A-A-002-17)
Page 65: Figure 7-37 Dual Monochrome 8-Bit Panel A.c. Timing
= [((REG[04h] bits [6:0]) + 1)∗8 - 1] Ts 5min 5. t = [((REG[05h] bits [4:0]) + 1)∗8 - 17] Ts 6min 6. t = [((REG[05h] bits [4:0]) + 1)∗8 - 8] Ts 7min EPSON 1-54 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 66: Dual Color 8-Bit Panel Timing
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)∗8Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-55 SPECIFICATION (X19A-A-002-17)
Page 67: Figure 7-39 Dual Color 8-Bit Panel A.c. Timing
= [((REG[04h] bits [6:0]) + 1)∗8 - 1] Ts 5min 5. t = [((REG[05h] bits [4:0]) + 1)∗8 - 18] Ts 6min 6. t = [((REG[05h] bits [4:0]) + 1)∗8 - 9] Ts 7min EPSON 1-56 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 68: Dual Color 16-Bit Panel Timing
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)∗8Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-57 SPECIFICATION (X19A-A-002-17)
Page 69 = [((REG[04h] bits [6:0]) + 1)∗8 - 1] Ts 5min 5. t = [((REG[05h] bits [4:0]) + 1)∗8 - 18] Ts 6min 6. t = [((REG[05h] bits [4:0]) + 1)∗8 - 9] Ts 7min EPSON 1-58 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 70: 16-Bit Tft Panel Timing
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) +1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts HNDP = Horizontal Non-Display Period = HNDP + HNDP = ((REG[05h] bits [4:0]) + 1)∗8Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-59 SPECIFICATION (X19A-A-002-17)
Page 71 = [((REG[04h] bits [6:0]) + 1)∗8] Ts 14min 9. t = [((REG[06h] bits [4:0]) + 1)∗8 - 2] Ts 15min 10. t = [((REG[05h] bits [4:0]) + 1)∗8 - ((REG[06h] bits [4:0]) + 1)∗8 + 2] 17min EPSON 1-60 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 72: Crt Timing
= (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8 Ts HNDP = Horizontal Non-Display Period = HNDP + HNDP = ((REG[05h] bits [4:0]) + 1)∗8 Ts EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-61 SPECIFICATION (X19A-A-002-17)
Page 73 7. t = [((REG[06h] bits [4:0]) + 1)∗8] Ts 12min 8. t = [((REG[04h] bits [6:0]) + 1)∗8] Ts 14min 9. t = [((REG[06h] bits [4:0]) + 1)∗8 - 2] Ts 15min EPSON 1-62 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 74: External Ramdac Read / Write Timing
DACRS[1:0] hold from AB[20:0], CS#, M/R# negated Valid RD# command to DACRS[1:0] delay DACRD# hold from valid RD# command negated Valid WR# command to DACWR# delay BCLK DACWR# pulse width low 2.45 T 2.55 T BCLK BCLK EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-63 SPECIFICATION (X19A-A-002-17)
Page 75: Registers
• REG[00h] is addressed when AB[5:0] = 0 • REG[01h] is addressed when AB[5:0] = 1 • REG[n] is addressed when AB[5:0] = n Memory access: the 2M byte display buffer is addressed by AB[20:0] × S1D13504 not selected EPSON 1-64 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 76: Register Descriptions
Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see “S1D13504 Programming Notes and Examples”, document number S19A-G-002-xx. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-65 SPECIFICATION (X19A-A-002-17)
Page 77: Panel/Monitor Configuration Registers
TFT LCD panels/CRTs the Horizontal Display Width must be divisible by 8. The maxi- mum horizontal display width is 1024 pixels. Note: This register must be programmed such that REG[04h] ≥ 3 (32 pixels) EPSON 1-66 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 78 HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1) × 8. The maximum HRTC pulse width is 128 pixels. Note: This register must be programmed such that (REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] + 1) EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-67 SPECIFICATION (X19A-A-002-17)
Page 79 VRTC/FPFRAME start position (lines) = VRTC/FPFRAME Start Position Bits [5:0] + 1. The maximum VRTC start delay is 64 lines. This register must be programmed such that Note: (REG[0Ah] bits [5:0] + 1) ≥ (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1) EPSON 1-68 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 80 VRTC/FPFRAME pulse width (lines) = VRTC/FPFRAME Pulse Width Bits [2:0] + 1. The maximum VRTC pulse width is 8 lines. Note: This register must be programmed such that (REG[0Ah] bits [5:0] + 1) ≥ (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1) EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-69 SPECIFICATION (X19A-A-002-17)
Page 81: Display Configuration Registers
“15/16 Bit-Per-Pixel Format Memory Organization,” on page 89 for a description of passive panel support. Table 8-7 Number of Bits-Per-Pixel Selection Number of Bits-Per-Pixel Select Bits [2:0] Number of Bits-Per-Pixel 110–111 Reserved EPSON 1-70 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 82 Note that this is a word address. An entry of 0000h into these registers rep- resents the ﬁrst word of display memory, an entry of 0001h represents the second word of display memory, and so on. See Section 10, “Display Conﬁguration” on page 88 for details. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-71 SPECIFICATION (X19A-A-002-17)
Page 83 A virtual image can be formed by setting this register to a value greater than the width of the display. The displayed image is a window into the larger virtual image. See Section 10, “Display Conﬁguration” on page 88 for details. EPSON 1-72 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 84 Section 4 for details. bits 7–4 Screen 2 Pixel Panning Bits [3:0] Pixel panning bits for screen 2. bits 3–0 Screen 1 Pixel Panning Bits [3:0] Pixel panning bits for screen 1. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-73 SPECIFICATION (X19A-A-002-17)
Page 85: Clock Configuration Register
These bits determine the amount of divide from the memory clock to generate the pixel clock (PCLK): Table 8-9 PCLK Divide Selection PCLK Divide Select Bits [1:0] MCLK/PCLK Frequency Ratio See Section 11.2, “Frame Rate Calculation” on page 92 for selection of PCLK fre- quency. EPSON 1-74 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 86: Power Save Configuration Registers
These bits should not be changed when suspend mode is enabled. bit 0 Software Suspend Mode Enable When this bit = 1 software suspend mode is enabled. When this bit = 0 software suspend mode is disabled. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-75 SPECIFICATION (X19A-A-002-17)
Page 87: Miscellaneous Registers
MD[15:0] Configuration Status These are read-only status bits for the MD[15:0] pins conﬁguration status at the rising edge of RESET#. See Table 5-8, “Summary of Power On / Reset Options,” on page 16. EPSON 1-76 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 88 0 GPIO0 Pin IO Configuration When this bit = 1, GPIO0 is conﬁgured as an output. When this bit = 0 (default), GPIO0 is conﬁgured as an input. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-77 SPECIFICATION (X19A-A-002-17)
Page 89 The MD8 pin must be high at the rising edge of RESET# to enable GPIO8, otherwise the DACRS0 pin is controlled automatically and this bit will have no effect on hardware. EPSON 1-78 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 90 When GPIO0 is conﬁgured as an output, a “1” in this bit drives GPIO0 to high and a “0” in this bit drives GPIO0 to low. When GPIO0 is conﬁgured as an input, a read from this bit returns the status of GPIO0. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-79 SPECIFICATION (X19A-A-002-17)
Page 91 GPIO8. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO8, otherwise the DACRS0 pin is controlled automatically and this bit will have no effect on hardware. EPSON 1-80 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 92 = 1 or 2 = (1.5) T if EDO and N = 1.5 = (N + 0.5) T if FPM and N = 1 or 2 = (N if FPM and N = 1.5 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-81 SPECIFICATION (X19A-A-002-17)
Page 93 When this bit = 0 the display FIFO is enabled. bits 4–0 Display FIFO Threshold Bits [4:0] These bits should be set to a value of 10h upon initialization as this provides the best overall performance for all display modes. EPSON 1-82 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 94: Look-Up Table Registers
For example: in a 16-level gray shade display mode, a data value of 0001b (4 bits-per- pixel) will point to Look-Up Table position one and display the 4-bit gray shade corre- sponding to the value programmed into that location. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-83 SPECIFICATION (X19A-A-002-17)
Page 95 In 8-bpp mode, the 16 position Green LUT is arranged into two, 8 position “banks.” Only bit 0 of these two bits controls which bank is currently selected. These bits have no effect in 1-bpp, 4-bpp, and 15/16-bpp modes. EPSON 1-84 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 96: External Ramdac Control Registers
The RAMDAC data must be transferred directly between the system data bus and the external RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-85 SPECIFICATION (X19A-A-002-17)
Page 97: Display Buffer
Image Buffer Half-Frame Buffer 17FFFFh 180000h Image Buffer Half-Frame Buffer Half-Frame Buffer 1FFFFFh Figure 9-1 Display Buffer Addressing The display buffer will contain an image buffer and may also contain a half-frame buffer. EPSON 1-86 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 98: Image Buffer
For example, for a 640 x 480 8 bpp color panel the half frame buffer size is 75K bytes. In a 512K byte display buffer, the half-frame buffer resides from 6D400h to 7FFFFh. In a 2M byte display buffer, the half-frame buffer resides from 1ED400h to 1FFFFFh. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-87 SPECIFICATION (X19A-A-002-17)
Page 99: Display Configuration
3-3-2 RGB bit 7 bit 0 Byte 0 Byte 1 n 2-0 n 2-0 n 1-0 = (R Byte 2 Panel Display Host Address Display Buffer Figure 10-1 1/2/4/8 Bit-Per-Pixel Format Memory Organization EPSON 1-88 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 100 Note: 1. The Host-to-Display mapping described here assumes that a Little-Endian interface is being used. 2. For 8/15/16 bit-per-pixel formats, Rn, Gn, Bn represent the red, green, and blue color compo- nents. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-89 SPECIFICATION (X19A-A-002-17)
Page 101: Image Manipulation
((REG[09h], REG[08h])+1) lines Screen 1 Line 0 Line 1 Screen 1 Line (REG[0Fh], REG[0Eh]) (REG[15h], REG[14h], REG[13h]) REG[18h] bits [7:4] Screen 2 Screen 2 ((REG[04h]+1)∗8) pixels (REG[17h], REG[16h]) Figure 10-3 Image Manipulation EPSON 1-90 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 102: Clocking
• Dual Color Panel with Half Frame Buffer Enabled. MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 • Simultaneous CRT + Dual Color Panel with Half Frame MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 Buffer Enable. MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-91 SPECIFICATION (X19A-A-002-17)
Page 103: Frame Rate Calculation
• Dual Mono with Half Frame 1/2/4/8/16 12.5 800×600 Buffer Enabled. 640×480 1/2/4/8/16 12.5 640×400 1/2/4/8/16 12.5 • Dual Color with Half Frame 1/2/4/8 12.5 800×600 Buffer Enabled. 8.33 640×480 1/2/4/8 12.5 8.33 EPSON 1-92 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 104 4. Optimum frame rates for panels range from 60Hz to 150Hz. If the maximum refresh rate is too high for a panel, MCLK should be reduced or PCLK should be divided down. 5. Half Frame Buffer disabled by REG[1Bh] bit 0. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-93 SPECIFICATION (X19A-A-002-17)
Page 105: Look -U P Table Architecture
4-bit display data output Select Select Bank 2 Logic Logic Bank 3 Bank Select bits [1:0] REG[27h] bits [1:0] 2-bit pixel data Figure 12-2 2 Bit-Per-Pixel – 4-Level Gray-Shade Mode Look-Up Table Architecture EPSON 1-94 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 106: Bit-Per-Pixel Mode
1-bit pixel data Green Look-Up Table Entry 4-bit Green data output Select Logic Blue Look-Up Table Entry 4-bit Blue data output Select Logic Figure 12-4 1 Bit-Per-Pixel – 2-Level Color Look-Up Table Architecture EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-95 SPECIFICATION (X19A-A-002-17)
Page 107 Entry Bank 4-bit Blue data output Select Select Bank 2 Logic Logic Bank 3 Bank Select bits [1:0] REG[27h] bits [3:2] Figure 12-5 2 Bit-Per-Pixel – 4-Level Color Mode Look-Up Table Architecture EPSON 1-96 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 108 0010 0011 0100 0101 Entry 0110 4-bit Blue data output 0111 Select 1000 Logic 1001 1010 1011 1100 1101 1110 1111 Figure 12-6 4 Bit-Per-Pixel – 16-Level Color Mode Look-Up Table Architecture EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-97 SPECIFICATION (X19A-A-002-17)
Page 109: Bit-Per-Pixel Color Mode
4-bit Blue data output Select Select Bank 2 Logic Logic Bank 3 Bank Select bits [1:0] REG[27h] bits [3:2] 2-bit pixel data Figure 12-7 8 Bit-Per-Pixel – 256-Level Color Mode Look-Up Table Architecture EPSON 1-98 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 110: Power Save Modes
• If suspend mode CBR refresh is selected, all internal modules and clocks except the Host Bus I/F and the Memory I/F are shut down. • If suspend mode self-refresh or no-refresh is selected, all internal modules and clocks except the Host Bus I/F are shut down. EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-99 SPECIFICATION (X19A-A-002-17)
Page 111: Power Save Mode Function Summary
REG[07h] bit 6 respectively. 2. Selectable: may be CBR refresh, self-refresh or no refresh at all. 3. DACWR#, DACRD#, DACRS0, DACRS1 are active but DACCLK is disabled. 4. Active for non-DAC register access only. EPSON 1-100 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 112 14: MECHANICAL DATA 14 M ECHANICAL 14.1 QFP15-128pin (S1D13504F00A) Unit: mm QFP15-128pin ±0.4 ±0.1 INDEX +0.1 0.16 –0.05 +0.05 0.125 –0.025 0° 10° ±0.2 Figure 14-1 Mechanical Drawing QFP15-128pin EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-101 SPECIFICATION (X19A-A-002-17)
Page 113 14: MECHANICAL DATA 14.2 TQFP15-128pin (S1D13504F01A) Unit: mm TQFP15-128pin ±0.4 ±0.1 INDEX +0.05 0.16 –0.03 +0.05 0.125 –0.025 0° 10° ±0.2 Figure 14-2 Mechanical Drawing TQFP15-128pin EPSON 1-102 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 114 14: MECHANICAL DATA 14.3 QFP20-144pin (S1D13504F02A) Unit: mm QFP20-144pin ±0.4 ±0.1 INDEX +0.1 –0.05 +0.05 0.125 –0.025 0° 10° ±0.2 Figure 14-3 Mechanical Drawing QFP20-144pin EPSON S1D13504 SERIES HARDWARE FUNCTIONAL 1-103 SPECIFICATION (X19A-A-002-17)
Page 115 14: MECHANICAL DATA THIS PAGE IS BLANK. EPSON 1-104 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17)
Page 117 5.5 LCD Enable/Disable Sequencing (REG[0D] bit 0) ..............2-22 6 CRT C ......................2-23 ONSIDERATIONS 6.1 Introduction..........................2-23 6.1.1 CRT Only ........................2-23 6.1.2 Simultaneous Display ....................2-24 S1D13504 ....................2-26 DENTIFYING THE (HAL).................2-27 ARDWARE BSTRACTION AYER 8.1 Introduction..........................2-27 EPSON S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 118 8.2.5 Register Manipulation....................2-37 8.2.6 Miscellaneous........................ 2-37 ........................2-38 AMPLE 9.1 Introduction ..........................2-38 9.1.1 Sample Code Using 13504HAL API................2-38 9.1.2 Sample Code Without Using 13504HAL API..............2-39 ..................2-43 PPENDIX UPPORTED ANEL ALUES EPSON 2-ii S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 119 8 bpp Recommended RAMDAC Palette Data for Simultaneous Display......2-24 Table 6-4 Related Register Data for Simultaneous Display ...............2-25 Table A-1 Passive Single Panel......................2-43 Table A-2 Passive Dual Panel ......................2-43 Table A-3 TFT Panel...........................2-43 EPSON S1D13504 PROGRAMMING NOTES 2-iii AND EXAMPLES (S19A-G-002-06)
Page 120: Introduction
The second half of this guide introduces the Hardware Abstraction Layer (HAL), designed to make programming the S1D13504 as easy as possible. Future S1D1350x products will support the HAL which will allow OEMs the ability to upgrade to future chips with relative ease. EPSON S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 121: Programming The S1D13504 Registers
DUAL bit set + (Horizontal resolution > 0) + HFB enabled (default power-on state). 2.1.5 REG[23] Display FIFO This register can be asynchronously enabled/disabled. Note: The Display FIFO starts to access DRAM after RESET. EPSON S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 122: Register Initialization
In addition, it is assumed that there is no external RAMDAC since only the LCD is being pro- grammed. Consequently, the RAMDAC registers are not programmed. For code examples, see Section 9, “Sample Code” on page 38. EPSON S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 123: Re-Programming Registers
2.2.3 Re-Programming Registers The only register which may require modiﬁcation after the initialization sequence is the Half Frame Buffer. The Memory Type, DUAL/SINGLE, and the Performance Register bits should never be modiﬁed after initialization. EPSON S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 124: Disabling The Half Frame Buffer Sequence
Waiting for 1 FRAME delay will guarantee that the Half Frame Buffer is idle. 4. Disable the Half Frame Buffer (REG[1B] bit 0 = 1). 5. Re-program the horizontal resolution to your original value. EPSON S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 125: Display Buffer Location
Four bit-per-pixel provides sixteen shades of gray by indexing into positions 0 through F of the Green LUT and 16 levels of color by indexing into positions 0 through F of the Red/Green/Blue LUTs. EPSON S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 126: Memory Organization For Eight Bit-Per-Pixel (256 Colors)
ﬁve bits for blue. The output bypasses the LUT and goes directly into the Frame Rate Modula- tor. Although 16 bit-per-pixel only make sense for a color panel, this memory model can be set on a monochrome panel, however only 16 shades of gray will be visible. EPSON S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 127: Look-Up Table (Lut)
In 2 bpp mode, the 16 entry LUTs are logically split into 4 groups of 4 entries for each of R, G, B. Bank 0 = Indexes 00–03h Bank 1 = Indexes 04–07h Bank 2 = Indexes 08–0Bh Bank 3 = Indexes 0C–0Fh EPSON S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 128: Look-Up Table Organization
Depending on the selected pixel size, these LUTs will provide from 1 to 4 banks. 1 bpp Color In 1 bpp color mode, the LUT is limited to a single 2 entry bank per color. The LUT bank select bits have no effect in this mode. EPSON S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 129 [1:0] represent the blue LUT index. It is recommended that the three LUTs are pro- grammed according to the following format: Table 3-11 Recommended LUT Values For 8 bpp Color Mode Address Green Blue bank 1 bank 1 bank 1 bank 1 EPSON 2-10 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 130 In 4 bpp gray shade mode, the pixel value indexes into one of 16 LUT entries. The LUT bank bits are ignored in this mode. The recommendation for this mode is to program the register values to data values equalling the register number (i.e. G[0] = 0, G[1]=1, G[2]=2, ... G[F]=0Fh). EPSON S1D13504 PROGRAMMING NOTES 2-11...
Page 131 Since the Look-Up Table is bypassed in this mode, the LUT programming is unimportant. The gray shades on the display are derived from the 4 most signiﬁcant bits of the Green component of the pixel data. Resulting in a maximum of 2 =16 colors. EPSON 2-12 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 132: Advanced Techniques
The for- mula to calculate the offset to write to these registers is: offset_register = pixels_per_line / pixels_per_word EPSON S1D13504 PROGRAMMING NOTES 2-13 AND EXAMPLES (S19A-G-002-06)
Page 133: Examples
512K bytes. It is safe to continue with these values. 4. Program the Memory Address Offset Registers. Register [17h] will be set to 0 and register [16h] will be set to 0xA0. EPSON 2-14 S1D13504 PROGRAMMING NOTES...
Page 134: Panning And Scrolling
This effect is barely noticeable at 8 bpp but becomes pro- nounced at 4 bpp, and lower, color depths. Setting the registers out of sequence will make the tear more apparent. EPSON S1D13504 PROGRAMMING NOTES 2-15...
Page 135: Registers
The following table shows this. Table 4-2 Active Pixel Pan Bits Color Depth (bpp) Pixel Pan Bits Used bits [3:0] bits [2:0] bits [1:0] bit 0 15/16 EPSON 2-16 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 136: Examples
2. Increment the start address by the number of words per virtual line. start_address = start_address + words 3. Separate the start address value into three bytes. Write the LSB to register [10h] and the MSB to register [12h]. EPSON S1D13504 PROGRAMMING NOTES 2-17 AND EXAMPLES (S19A-G-002-06)
Page 137: Split Screen
Bit 18 Bit 17 Bit 16 These three registers form the twenty bit offset to the ﬁrst word in display buffer that will be shown in the screen 2 portion of the display. EPSON 2-18 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 138: Examples
4. Set the screen 2 start address to the value we just calculated. Write the screen 2 start address registers [13h], [14h] and [15h] with the values 0x60, 0x3B and 0x00 respectively. EPSON S1D13504 PROGRAMMING NOTES 2-19 AND EXAMPLES (S19A-G-002-06)
Page 139: Lcd Power Sequencing And Power Save Modes
See the “S1D13504 Hardware Functional Speciﬁcation”, document number S19A-A-002-xx. All other bits should be masked into the register on a write. i.e. do a read, modify with mask, and write to set the bits. EPSON 2-20 S1D13504 PROGRAMMING NOTES...
Page 140: Suspend Sequencing
5.4.2 Suspend Disable Sequence Disable Suspend (either {REG[1A] bit 0 = 0, or SUSPEND# pin inactive): LCDPWR# and FPFRAME will start within 1 frame, while the remaining LCD interface signals will start immedi- ately. EPSON S1D13504 PROGRAMMING NOTES 2-21 AND EXAMPLES (S19A-G-002-06)
Page 141: Lcd Enable/Disable Sequencing (Reg[0D] Bit 0)
LCDPWR#). If 128 frames is not enough 'time' to allow the LCD Drive power supply to decay to 0V, LCDPWR# can be controlled manually using REG[1A] bit 3. EPSON 2-22 S1D13504 PROGRAMMING NOTES...
Page 142: Crt Considerations
0000 0000 0000 0000 0000 0000 0000 0000 set MCLK and PCLK divide REG[2Ch] 0000 0000 0000 0000 0000 0000 0000 0000 set write mode address to 0 REG[2Eh] load RAMDAC palette data EPSON S1D13504 PROGRAMMING NOTES 2-23 AND EXAMPLES (S19A-G-002-06)
Page 143: Simultaneous Display
8 bpp Simultaneous Display. Table 6-4 shows the related register data for some possible CRT options with an 8-bit Color 640x480 single passive panel. Table 6-3 8 bpp Recommended RAMDAC Palette Data for Simultaneous Display Address Address Address Address EPSON 2-24 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 144 0 REG[26h] load look-up table REG[27h] 0000 0000 0000 0000 set look-up table to bank 0 REG[2Ch] program RAMDAC program RAMDAC set write mode address to 0 REG[2Eh] load RAMDAC palette data EPSON S1D13504 PROGRAMMING NOTES 2-25 AND EXAMPLES (S19A-G-002-06)
Page 145: Identifying The S1D13504
Unlike previous generations of S1D1350x products, the S1D13504 can be identiﬁed at any time after power on / reset. The S1D13504 and future S1D1350x products can be identiﬁed by reading REG[00h]. The value of this register for the S1D13504 is 04h. EPSON 2-26 S1D13504 PROGRAMMING NOTES...
Page 146: Hardware Abstraction Layer (Hal)
AYER 8.1 Introduction The HAL is a processor independent programming library provided by Seiko Epson. HAL provides an easy method to program and conﬁgure the S1D13504. HAL allows easy porting from one S1D1350x product to another and between system architectures. HAL is included in the utilities provided with the S1D13504 evaluation system.
Page 147 Determines if the device handle is HAL_STDOUT or HAL_STDIN. Parameter: device - registered device ID Return Value: ERR_OK - operation completed with no problems. ERR_HAL_DEVICE_ERR - could not find free device handle. EPSON 2-28 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 148: Screen Manipulation
Parameter: device - registered device ID pDispLogicalAddr - logical address is returned in this variable. Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. EPSON S1D13504 PROGRAMMING NOTES 2-29 AND EXAMPLES (S19A-G-002-06)
Page 149 - desired number of bpp Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_COULD_NOT_GET_VALUE - value read from registers is invalid. ERR_HAL_BAD_ARG - argument BitsPerPixel is invalid. EPSON 2-30 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 150 = 16. Note: seSetInit() must have been called before calling seVirtInit(). This is because the VNDP is used for timing, and this would not be possible if the registers were not first initialized. EPSON S1D13504 PROGRAMMING NOTES 2-31...
Page 151 - offset from start of the display buffer - value to write count - number of dwords to write Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. EPSON 2-32 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 152: Color Manipulation
- pointer to an array of BYTE entry[3] entry[x][0] == RED component entry[x][1] == GREEN component entry[x][2] == BLUE component Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. EPSON S1D13504 PROGRAMMING NOTES 2-33 AND EXAMPLES (S19A-G-002-06)
Page 153 - pointer to an array of BYTE entry[3] entry[x][0] == RED component entry[x][1] == GREEN component entry[x][2] == BLUE component Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. EPSON 2-34 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 154: Drawing
- operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_INVALID_STD_DEVICE - device is not HAL_STDOUT or HAL_STDIN (but don't use HAL_STDIN for seDrawText()). Note: seDrawText() currently doesn't write text to the display buffer. EPSON S1D13504 PROGRAMMING NOTES 2-35 AND EXAMPLES (S19A-G-002-06)
Page 155 - for 1,2,4,8 bpp: refers to index into LUT/DAC. For 15,16 bpp: defines color directly (not LUT/DAC index). Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. EPSON 2-36 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 156: Register Manipulation
Rotates the bits in “val” right as many times as stated in “bits”. Parameter: - value to rotate bits - how many bits to rotate Return Value: bits 15–8: non-zero if carry flag set bits 7–0: rotated byte EPSON S1D13504 PROGRAMMING NOTES 2-37 AND EXAMPLES (S19A-G-002-06)
Page 157: Sample Code
13504HAL API. These code samples are for example purposes only. 9.1.1 Sample Code Using 13504HAL API **------------------------------------------------------------------------- Sample Code using 1354HAL API Copyright (c) Seiko Epson Corp. 1998. All rights reserved. **------------------------------------------------------------------------- #include <stdio.h> #include <stdlib.h>...
Page 158: Sample Code Without Using 13504Hal Api
3) The pointer assignment for the register offset does not work on Intel 16 bit platforms. **--------------------------------------------------------------------------- Created 1998, Epson Research & Development Vancouver Design Centre Copyright (c) 1998 Epson Research and Development, Inc. All rights reserved. **--------------------------------------------------------------------------- $Header: $Revision: $...
Page 159 /* 0000 0000 */ ** Register A: Vertical Non-Display Period (VNDP) This register must be programed with register 5 (HNDP) to arrive at the frame rate closest to the desired frame rate. EPSON 2-40 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 160 *(pRegs + 0x20) = 0x00; /* 0000 0000 */ *(pRegs + 0x21) = 0x00; /* 0000 0000 */ ** Registers 24-27: LUT control. For this example do a typical 8BPP LUT setup. EPSON S1D13504 PROGRAMMING NOTES 2-41 AND EXAMPLES (S19A-G-002-06)
Page 161 ** Register 23: Performance Enhancement - display FIFO enabled, optimum performance. *(pRegs + 0x23) = 0x10; /* 0001 0000 */ ** Register D: Display Mode - 8 BPP, LCD enable. *(pRegs + 0x0D) = 0x0D; /* 0000 1101 */ EPSON 2-42 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 162: Appendix Supported Panel Values
REG[19h] 0000 0001 set MCLK and PCLK divide REG[24h] 0000 0000 set Look-Up Table address to 0 REG[26h] load LUT load Look-Up Table REG[27h] 0000 0000 set Look-Up Table to bank 0 EPSON S1D13504 PROGRAMMING NOTES 2-43 AND EXAMPLES (S19A-G-002-06)
Page 163 APPENDIX: SUPPORTED PANEL VALUES THIS PAGE IS BLANK. EPSON 2-44 S1D13504 PROGRAMMING NOTES AND EXAMPLES (S19A-G-002-06)
Page 165 5.2 Installation ...........................3-20 5.3 Usage ............................3-20 5.4 13504PLAY Example ........................3-22 5.5 Scripting ............................3-22 5.6 Comments ...........................3-22 5.7 Program Messages ........................3-23 6 13504BMP D .................3-24 EMONSTRATION ROGRAM 6.1 Installation ...........................3-24 6.2 Usage ............................3-24 6.3 Comments ...........................3-24 6.4 Program Messages ........................3-25 EPSON UTILITIES (S19A-B-001-03)
Page 166 CONTENTS 7 13504PWR S ..........3-26 OFTWARE USPEND OWER EQUENCING TILITY 7.1 S1D13504 Supported Evaluation Platforms................3-26 7.2 Installation ........................... 3-26 7.3 Usage............................3-26 7.4 Comments........................... 3-27 7.5 Program Messages ........................3-27 EPSON 3-ii UTILITIES (S19A-B-001-03)
Page 167 13504CFG LUT Setup......................3-11 Figure 1-21 13504CFG Edit LUT Setup ....................3-11 Figure 1-22 13504CFG LUT Parameter Edit ..................3-11 Figure 1-23 13504CFG Setup .......................3-12 Figure 1-24 13504CFG Setup Parameter Edit For Register Location, Memory Location, and Memory Size .......................3-12 EPSON UTILITIES (S19A-B-001-03) 3-iii...
Page 168: 13504Cfg.exe Configuration Program
Copy the following ﬁles to a directory that is in the DOS path on your hard drive: • 13504CFG.EXE • G032.EXE • OBJCOPY.EXE Note: G032.EXE and OBJCOPY.EXE are called by 13504CFG.EXE for non-Intel platforms. Neither pro- gram is intended to run independent of 13504CFG. EPSON UTILITIES (S19A-B-001-03)
Page 169: Usage
In this example, all of the other panel settings in the 13504 utility remain the same. In general, how- ever, it is necessary to set several more panel parameters before the panel is properly conﬁgured. The full list of all the possible parameters to 13504CFG is included in the ﬁle 13504.INI. EPSON UTILITIES (S19A-B-001-03)
Page 170: Interactive Mode
• Press <Tab> to highlight the Files box (or press <Alt><F>). Press < ↓ > to highlight 13504SHOW.EXE. Press <Enter>. All selections in 13504CFG can be made in one of the three ways listed above. Figure 1-2 13504CFG Open File EPSON UTILITIES (S19A-B-001-03)
Page 171: Files Menu
• Save All - saves modiﬁcations to all 13504 ﬁles that are in the same directory as the ﬁle being saved. This function ensures that the display parameters are consistent. “Save All” is only avail- able for utilities run on an Intel (EXE) platform. • Exit - exits the 13504CFG application. EPSON UTILITIES (S19A-B-001-03)
Page 172: View Menu
ﬁcation” manual, document number S19A-A-002-xx, and the “S1D13504 Programming Notes and Examples” manual, document number S19A-G-002-xx for formulas and other information. Note: Seiko Epson Corp. cannot be held liable for damage done to the display as a result of software con- figuration errors.
Page 173: Device Menu
1.5.4 Device Menu Figure 1-7 13504CFG Device Menu The Device menu contains the following sub-menus where parameters for a S1D13504 utility can be edited: • Panel • CRT • Advanced Memory • Power Management • Lookup Table • Setup EPSON UTILITIES (S19A-B-001-03)
Page 174 When a selection is highlighted for editing in the Edit Panel Setup window and Edit is clicked, the Panel Parameter Edit window displays for parameter editing. See Figure 1-10, “13504CFG Panel Parameter Edit” below. In this example window, “X Resolution: 320 pixels” can be edited. Figure 1-10 13504CFG Panel Parameter Edit EPSON UTILITIES (S19A-B-001-03)
Page 175 When a selection is highlighted for editing in the Edit CRT Setup window and Edit is clicked, the CRT Parameter Edit window displays for parameter editing. See Figure 1-13, “13504CFG CRT Parameter Edit” below. In this example window, “Horiz Non-Display: 240 pixels” can be edited. Figure 1-13 13504CFG CRT Parameter Edit EPSON UTILITIES (S19A-B-001-03)
Page 176 When a selection is highlighted for editing in the Edit Advanced Memory Setup window and Edit is clicked, the Memory Parameter Edit window is displayed for parameter editing. See Figure 1-16, “13504CFG Memory Parameter Edit” below. In this example window, “Refresh Time: 4000 Cycles” can be edited. Figure 1-16 13504CFG Memory Parameter Edit EPSON UTILITIES (S19A-B-001-03)
Page 177 When a selection is highlighted for editing in the Edit Power Setup window and Edit is clicked, the Power Parameter Edit window displays for parameter editing. See Figure 1-19, “13504CFG Power Parameter Edit” below. In this example window, “Suspend Refresh: CBR Refresh” can be edited. Figure 1-19 13504CFG Power Parameter Edit EPSON 3-10 UTILITIES (S19A-B-001-03)
Page 178 When a selection is highlighted for editing in the Edit LUT Setup window and Edit is clicked, the LUT Parameter Edit window displays for parameter editing. See Figure 1-22, “13504CFG LUT Parameter Edit” below. In this example window, “Bits Per Pixel: 2” can be edited. Figure 1-22 13504CFG LUT Parameter Edit EPSON UTILITIES (S19A-B-001-03) 3-11...
Page 179: Help Menu
There are three ﬁles in the Help menu. • Help: not available in this version of 13504CFG. • Help on Help: not available in this version of 13504CFG. • About: displays copyright and program version information. EPSON 3-12 UTILITIES (S19A-B-001-03)
Page 180: Comments
ILLEGAL VALUE: Choose between 8 and 800, in multiples of 8 pixels. The user entered an invalid number when changing the Panel X Resolution. ERROR: Failed to open the file! The selected program does not have the HAL structure, therefore cannot be opened by 13504CFG. EPSON UTILITIES (S19A-B-001-03) 3-13...
Page 181: 13504Show Demonstration Program
?? can be: 1, 2, 4, 8, 15, or 16 automatically cycles through all video modes /lcd displays on the LCD panel /crt displays on the CRT /vertical displays vertical line pattern displays the help screen /noinit bypasses register initialization EPSON 3-14 UTILITIES (S19A-B-001-03)
Page 182: Comments
13504CFG conﬁguration program. ERROR: Did not detect S1D13504. The HAL was unable to read the revision code register on the S1D13504. Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly. EPSON UTILITIES (S19A-B-001-03) 3-15...
Page 183: 13504Splt Display Utility
Screen 2 up ↓ moves Screen 2 down HOME covers Screen 1 with Screen 2 displays only Screen 1 Automatic mode: Z changes the direction of split-screen movement Both modes: changes the color depth (bits-per-pixel) exits 13504SPLT EPSON 3-16 UTILITIES (S19A-B-001-03)
Page 184: 13504Splt Example
13504CFG conﬁguration program. ERROR: Did not detect S1D13504. The HAL was unable to read the revision code register on the S1D13504. Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly. EPSON UTILITIES (S19A-B-001-03) 3-17...
Page 185: 13504Virt Display Utility
8 and less than 1024 (the default width is 1024 pixels); the maximum height is based on the dis- play memory and the width of the virtual display EPSON 3-18 UTILITIES (S19A-B-001-03)
Page 186: 13504Virt Example
13504CFG conﬁguration program. ERROR: Did not detect S1D13504. The HAL was unable to read the revision code register on the S1D13504. Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly. EPSON UTILITIES (S19A-B-001-03) 3-19...
Page 187: 13504Play Diagnostic Utility
Embedded platform: download the program 13504PLAY to the system. 5.3 Usage PC platform: at the prompt, type 13504play [/?]. Embedded platform: execute 13504play and at the prompt, type the command line argument. Where: /? displays program revision information. EPSON 3-20 UTILITIES (S19A-B-001-03)
Page 188 - Halts after lines of display. This feature halts the display during long read operations to prevent data from scrolling off the dis- play. - Set 0 to disable. - Quits this utility. - Displays Help information. EPSON UTILITIES (S19A-B-001-03) 3-21...
Page 189: 13504Play Example
CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. EPSON 3-22 UTILITIES (S19A-B-001-03)
Page 190 There are too many display devices attached to the HAL. The HAL can only manage 10 devices simultaneously. ERROR: Could not register S1D13504F00A device. A 13504 device was not found at the conﬁgured addresses. Check the conﬁguration address using the 13504CFG conﬁguration program. EPSON UTILITIES (S19A-B-001-03) 3-23...
Page 191 CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the S1D13504 when a CRT is also attached. EPSON 3-24 UTILITIES (S19A-B-001-03)
Page 192: Program Messages
13504CFG conﬁguration program. ERROR: Did not detect S1D13504. The HAL was unable to read the revision code register on the S1D13504. Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly. EPSON UTILITIES (S19A-B-001-03) 3-25...
Page 193: Installation
Embedded platform: execute 13504pwr and at the prompt, type the command line argument. Where: /software selects software suspend /lcd selects the LCD /enable activates software suspend or the LCD /disable deactivates software suspend or the LCD initializes registers displays this usage message EPSON 3-26 UTILITIES (S19A-B-001-03)
Page 194 13504CFG conﬁguration program. ERROR: Did not detect S1D13504. The HAL was unable to read the revision code register on the S1D13504. Ensure that the S1D13504 hardware is installed and that the hardware platform has been set up correctly. EPSON UTILITIES (S19A-B-001-03) 3-27...
Page 195 7: 13504PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY THIS PAGE IS BLANK. EPSON 3-28 UTILITIES (S19A-B-001-03)
Page 197 6.13 Adjustable LCD Panel Negative Power Supply ................4-9 6.14 Adjustable LCD Panel Positive Power Supply ................4-9 6.15 CPU/Bus Interface Header Strips....................4-9 6.16 Schematic Notes ...........................4-9 ...........................4-10 ARTS ......................4-11 CHEMATIC IAGRAMS EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 198 LCD Signal Connector (J6) ....................4-3 Table 4-1 CPU/BUS Connector (H1) Pinout ..................4-4 Table 4-2 CPU/BUS Connector (H2) Pinout ..................4-5 Table 5-1 Host Bus Interface Pin Mapping ..................4-6 EPSON 4-ii S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 199: Introduction
• On-board adjustable LCD BIAS negative power supply (-14V to -24V). • On-board adjustable LCD BIAS positive power supply (+23V to +40V). • CPU/Bus interface header strips for non-ISA bus support. EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 200: Installation And Configuration
Support for all panels which require Support for 8-bit panels which require DRDY signal selection MOD/DRDY signal 2 shift clocks = default settings for ISA bus and LCD panel support. EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 201 BLANK# DACCLK PCLK 2–26 (Even Pins) +12V +12V +12V +12V +12V +12V +12V +12V +12V DRDY DRDY DRDY DRDY FPSHIFT2 LCDPWR LCDPWR# LCDPWR# LCDPWR# LCDPWR# LCDPWR# LCDPWR# LCDPWR# LCDPWR# LCDPWR# EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 202: Cpu/Bus Interface Connector Pinouts
Connected to WE0# of the S1D13504 Connected to WAIT# of the S1D13504 Connected to CS# of the S1D13504 Connected to MR# of the S1D13504 Connected to WE#1 of the S1D13504 Not connected EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 203 Connected to RD/WR# of the S1D13504 Connected to BS# of the S1D13504 Connected to BUSCLK of the S1D13504 Connected to RD# of the S1D13504 Connected to AB20 of the S1D13504 Not connected EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 204: Host Bus Interface Pin Mapping
Connect to IO V RD/WR# RD/WR# R/W# R/W# RD1# Connect to IO V SIZ1 RD0# WE0# WE0# Connect to IO V SIZ0 WE0# WAIT# WAIT# DTACK# DSACK1# WAIT# RESET# RESET# RESET# RESET# RESET# EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 205: Technical Description
S1D13504 being configured as a 16-bit device (default, power-up), with the ISA Bus interface (supported through the PAL (U4)) configured for an 8-bit interface. The Epson supplied software performs this function automatically. 6.2 Non-ISA Bus Support This evaluation board is speciﬁcally designed to support the standard 16-bit ISA bus, however, the...
Page 206: Decode Logic
Refer to the section “Display Support” of the “S1D13504 Hardware Functional Speciﬁca- tion,” document number S19A-A-002-xx for details. The overlay function and sprite/hardware cursor display features are not supported. EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 207: Core V Dd Power Supply
Hardware Functional Speciﬁcation,” document number S19A-A-002-xx. 6.16 Schematic Notes The following schematics are for reference only and may not reflect actual implementation. Please request updated information before starting any hardware design. EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 208: Parts List
BrookTree RAMDAC PLCC package, 44-pin PLCC SMT part RD-0412 XENTECK - Positive Power Supply EPN001 XENTECK - Negative Power Supply LP2960AIN-3.3 National 3.3V Fixed Voltage Regulator N16G 16-PIN DIP package EPSON 4-10 S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 209: Schematic Diagrams
8: SCHEMATIC DIAGRAMS CHEMATIC IAGRAMS Figure 8-1 S5U13504P00C Schematic Diagram (1 of 6) EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD 4-11 USER’S MANUAL (S19A-G-004-05)
Page 210 8: SCHEMATIC DIAGRAMS Figure 8-2 S5U13504P00C Schematic Diagram (2 of 6) EPSON 4-12 S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 211 8: SCHEMATIC DIAGRAMS Figure 8-3 S5U13504P00C Schematic Diagram (3 of 6) EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD 4-13 USER’S MANUAL (S19A-G-004-05)
Page 212 8: SCHEMATIC DIAGRAMS Figure 8-4 S5U13504P00C Schematic Diagram (4 of 6) EPSON 4-14 S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 213 8: SCHEMATIC DIAGRAMS Figure 8-5 S5U13504P00C Schematic Diagram (5 of 6) EPSON S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD 4-15 USER’S MANUAL (S19A-G-004-05)
Page 214 8: SCHEMATIC DIAGRAMS Figure 8-6 S5U13504P00C Schematic Diagram (6 of 6) EPSON 4-16 S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05)
Page 216 4.3.1 Bus Interface Modes ......................5-27 4.3.2 Generic Bus Interface Mode ..................5-28 4.4 MPC821/S1D13504 Interface .....................5-29 4.4.1 Hardware Connections ....................5-29 4.4.2 S1D13504 Hardware Configuration ................5-31 4.4.3 MPC821 Chip Select Configuration ................5-32 4.4.4 Test Software.........................5-33 4.5 References ..........................5-34 EPSON APPLICATION NOTES (S19A-G-005-05)
Page 217 6.3.2 Hardware Description—Using Two IT8368E’s .............. 5-48 6.3.3 IT8368E Configuration....................5-49 6.3.4 Memory Mapping and Aliasing ..................5-49 6.3.5 S1D13504 Configuration ....................5-50 6.4 Software ............................5-51 ......................5-52 OWER ONSUMPTION 7.1 S1D13504 Power Consumption....................5-52 7.1.1 Conditions........................5-53 7.2 Summary............................. 5-53 EPSON 5-ii APPLICATION NOTES (S19A-G-005-05)
Page 218 TX3912 to PC Card Slots Address Remapping using the IT8368E ........5-49 Table 6-5 S1D13504 Configuration using the IT8368E..............5-50 Table 6-6 S1D13504 Generic MPU Host Bus Interface Pin Mapping ..........5-50 Table 7-1 S1D13504 Total Power Consumption ................5-53 EPSON APPLICATION NOTES (S19A-G-005-05) 5-iii...
Page 219: Interfacing To The Philips Mips Pr31500/Pr31700 Processor
• System design using one ITE8368E PC Card/GPIO buffer chip (see Section 1.3.1, “Hardware Description—Using One IT8368E” on page 4). • System design using two ITE8368E PC Card/GPIO buffer chips (see Section 1.3.2, “Hardware Description—Using Two IT8368E’s” on page 5). EPSON APPLICATION NOTES (S19A-G-005-05)
Page 220: Direct Connection To The Philips Pr31500/Pr31700
DCLKOUT (divided) as the clock source, should be based on the desired: • pixel and frame rates. • power budget. • part count. • maximum S1D13504 clock frequencies. The S1D13504 also has internal clock dividers providing additional ﬂexibility. EPSON APPLICATION NOTES (S19A-G-005-05)
Page 221: Memory Mapping And Aliasing
When the S1D13504 is conﬁgured for Generic MPU host bus interface, the host interface pins are mapped as in the table below. Table 1-2 S1D13504 Generic MPU Host Bus Interface Pin Mapping Pin Name Pin Function WE1# WE1# Connect to IO V RD/WR# RD1# RD0# WE0# WE0# EPSON APPLICATION NOTES (S19A-G-005-05)
Page 222: System Design Using The It8368E Pc Card Buffer
IT8368E. This makes the S1D13504 virtually transparent to PC Card devices that use the same slot. 1.3.1 Hardware Description—Using One IT8368E The ITE IT8368E has been speciﬁcally designed to support EPSON CRT/LCD controllers. The IT8368E provides eleven Multi-Function IO pins (MFIO). Conﬁguration registers can be used to allow these MFIO pins to provide the control signals required to implement the S1D13504 CPU interface.
Page 223 DCLKOUT (divided) as the clock source, should be based on the desired: • pixel and frame rates. • power budget. • part count. • maximum S1D13504 clock frequencies. The S1D13504 also has internal clock dividers providing additional ﬂexibility. EPSON APPLICATION NOTES (S19A-G-005-05)
Page 224: It8368E Configuration
8M byte aliased 131,072 times at 64 byte intervals S1D13504 display buffer, 0D80 0000h 8M byte aliased 4 times at 2Mb intervals 0E00 0000h 32M byte Card 2 Attribute 6800 0000h 64M byte Card 2 Memory EPSON APPLICATION NOTES (S19A-G-005-05)
Page 225: S1D13504 Configuration
When the S1D13504 is conﬁgured for Generic MPU host bus interface, the host interface pins are mapped as in the table below. Table 1-6 S1D13504 Generic MPU Host Bus Interface Pin Mapping Pin Name Pin Function WE1# WE1# Connect to IO V RD/WR# RD1# RD0# WE0# WE0# EPSON APPLICATION NOTES (S19A-G-005-05)
Page 226: Software
The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The S1D13504 test utilities and Windows CE v2.0 display drivers are available from your sales sup- port contact or www.erd.epson.com. EPSON APPLICATION NOTES (S19A-G-005-05)
Page 227: Interfacing To The Nec V R 4102 Tm Microprocessor
Pull-up LCDRDY WAIT# M/R# RSOUT RESET# ADD[25:0] AB[20:0] DAT[15:0] DB[15:0] BUSCLK BUSCLK Note: The propagation delay of the Read/write Decode Logic shown above must be less than 10 nsec. Figure 2-1 NEC V 4102 Configuration Schematic EPSON APPLICATION NOTES (S19A-G-005-05)
Page 228: Hardware Description
16-bit Read RD0# = low RD1# - low 8-bit even address Write WR0# = low WR1# = high 8-bit odd address Write WR0# = high WR1# = low 16-bit Write WR0# = low WR1# = low EPSON 5-10 APPLICATION NOTES (S19A-G-005-05)
Page 229: Software
2: INTERFACING TO THE NEC V 4102TM MICROPROCESSOR 2.3 Software Epson provides software source code for both the test utilities and the Windows CE 2.0 display driver. The test utilities are conﬁgurable for different panel types using an MS-DOS program called 13504CFG, or by modifying the source.
Page 230: Interfacing To The Pc Card Bus
The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Research and Development Website at http://www.erd.epson.com for the latest revision of this docu- ment before beginning any development.
Page 231: Interfacing To The Pc Card Bus
During a read cycle, OE# (output enable) is driven low. A write cycle is speciﬁed by driving OE# high and driving the write enable signal (WE#) low. The cycle can be lengthened by driving WAIT# low for the time needed to complete the cycle. EPSON APPLICATION NOTES (S19A-G-005-05) 5-13...
Page 232 Hi-Z DATA VALID Transfer Start Transfer Complete Figure 3-1 PC Card Read Cycle A[25:0] ADDRESS VALID REG# CE1# CE2# WAIT# Hi-Z Hi-Z D[15:0] DATA VALID Transfer Start Transfer Complete Figure 3-2 PC Card Write Cycle EPSON 5-14 APPLICATION NOTES (S19A-G-005-05)
Page 233: S1D13504 Host Bus Interface
The capability to select the endian mode independent of the host bus interface offers more ﬂexibility in conﬁguring the S1D13504 with other CPUs. For details on conﬁguration, refer to the “S1D13504 Hardware Functional Speciﬁcation”, document number S19A-A-002-xx. EPSON APPLICATION NOTES (S19A-G-005-05) 5-15...
Page 234: Generic Mpu Host Bus Interface
MD5 if the host CPU wait state signal is active high. • The Bus Start (BS#) signal is not used for the Generic MPU host bus interface and should be tied low (connected to GND). EPSON 5-16 APPLICATION NOTES (S19A-G-005-05)
Page 235: Pc Card To S1D13504 Interface
PC Card socket PAL16L8-10 S1D13504 RD/WR# CE1# WE0# CE2# WE1# REG# RESET RESET# M/R# A[21:0] AB[20:0] D[15:0] DB[15:0] 15K pull-up WAIT# WAIT# BUSCLK CLKI Oscillator Figure 3-3 Typical Implementation of PC Card to S1D13504 Interface EPSON APPLICATION NOTES (S19A-G-005-05) 5-17...
Page 236: S1D13504 Hardware Configuration
; /pcreg means disable in attribute mode we1 = we * ce2 * /pcreg ; /pcreg means disable in attribute mode cs = rd0 + rd1 + we0 + we1 reset = breset ; inversion appears in pin declaration ; section EPSON 5-18 APPLICATION NOTES (S19A-G-005-05)
Page 237: Register/Memory Mapping
Since address bits A[25:22] are ignored, the S1D13504 registers and display buffer are aliased 16 times. Note: If aliasing is not desirable, the upper addresses must be fully decoded. EPSON APPLICATION NOTES (S19A-G-005-05) 5-19...
Page 238: Software
The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The S1D13504 test utilities and Windows CE v2.0 display drivers are available from your sales sup- port contact or on the internet at http://www.erd.epson.com. EPSON 5-20...
Page 239: References
• “S1D13504 Programming Notes and Examples”, Document Number S19A-G-002-xx. • “S5U13504P00C Rev. 1.0 ISA Bus Evaluation Board User’s Manual”, Document Number S19A- G-004-xx. 3.6.2 Document Sources • PC Card Website: http://www.pc-card.com. • Epson Research and Development Website: http://www.erd.epson.com. EPSON APPLICATION NOTES (S19A-G-005-05) 5-21...
Page 240: Interfacing To The Motorola Mpc821 Microprocessor
The MPC821 can generate up to eight independent chip select outputs, each of which may be con- trolled by one of two types of timing generators, the General Purpose Chip Select Module (GPCM) or the User-Programmable Machine (UPM). Examples are given using the GPCM. EPSON 5-22 APPLICATION NOTES (S19A-G-005-05)
Page 241: Interfacing To The Mpc821
1. An option in the clock control register allows the external bus to run at one-half the CPU core speed; this is typically used when the CPU core is operated above 50 MHz. EPSON APPLICATION NOTES (S19A-G-005-05) 5-23...
Page 242 Transfer Next Transfer Complete Starts Figure 4-1 Power PC Memory Read Cycle SYSCLK A[0:31] RD/WR TSIZ[0:1], AT[0:3] D[0:31] Valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 4-2 Power PC Memory Write Cycle EPSON 5-24 APPLICATION NOTES (S19A-G-005-05)
Page 243 S1D13504 address space; this support is included in the example inter- faces. 1. This assumes that the Power PC core is operating in big endian mode, which is the typical case for embedded systems. EPSON APPLICATION NOTES (S19A-G-005-05) 5-25...
Page 244: Memory Controller Module
In this application note, the GPCM is used instead of the UPM, since the GPCM has enough ﬂexibil- ity to accommodate the S1D13504 and it is desirable to leave the UPMs free to handle other inter- facing duties, such as EDO DRAM. EPSON 5-26 APPLICATION NOTES (S19A-G-005-05)
Page 245: S1D13504 Bus Interface
REG[1Bh] clears this bit to 0. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging. EPSON APPLICATION NOTES (S19A-G-005-05) 5-27...
Page 246: Generic Bus Interface Mode
MD5 at reset. • The Bus Status (BS#) signal is unused in general purpose bus mode, and should be tied high (con- nected to IO V EPSON 5-28 APPLICATION NOTES (S19A-G-005-05)
Page 247: Mpc821/S1D13504 Interface
SD[15:0] 470 pull-up WAIT# WE1# WE0# RD1# RD0# SYSCLK BUSCLK RESET RESET# Figure 4-3 Block Diagram of MPC821/S1D13504 Interface Table 4-1 details the connections between the pins and signals of the MPC821 and the S1D13504. EPSON APPLICATION NOTES (S19A-G-005-05) 5-29...
Page 248 P12-A4, P12-B4, P12-A5, P12-B5, P12-A6, P12-B6, P12-A7 #1 Note that the bit numbering of the Power PC bus signals is reversed from convention, e.g.: the most significant address bit is A0, the next is A1, A2, etc. EPSON 5-30 APPLICATION NOTES (S19A-G-005-05)
Page 249: S1D13504 Hardware Configuration
Generic bus interface (e.g. MPC821, ISA bus interface) Reserved = required settings for MPC821 support. Table 4-4 Memory Conﬁguration Option Memory Selection Symmetrical 256K x 16 DRAM Symmetrical 1M x 16 DRAM Asymmetrical 256K x 16 DRAM Asymmetrical 1M x 16 DRAM EPSON APPLICATION NOTES (S19A-G-005-05) 5-31...
Page 250: Mpc821 Chip Select Configuration
• SCY (0:3) = 0 – wait state selection; this ﬁeld is ignored since external transfer acknowledge is used; see SETA below • SETA = 1 – the S1D13504 generates an external transfer acknowledge using the WAIT# line • TRLX = 0 – normal timing • EHTR = 0 – normal timing EPSON 5-32 APPLICATION NOTES (S19A-G-005-05)
Page 251: Test Software
MPC821 does not attempt to cache any data read from or written to the S1D13504 or its display refresh buffer. 1. MPC8BUG does not support comments or symbolic equates; these have been added for clarity. EPSON APPLICATION NOTES (S19A-G-005-05) 5-33...
Page 252: References
• “S5U13504P00C Rev. 1.0 ISA Bus Evaluation Board User’s Manual”; Document Number S19A- G-004-xx, • “S1D13504 Programming Notes and Examples”; Document Number S19A-G-002-xx 4.5.2 Document Sources • Motorola Inc.: Motorola Literature Distribution Center, (800) 441-2447. • EPSON Research and Development web page: www.erd.epson.com EPSON 5-34 APPLICATION NOTES (S19A-G-005-05)
Page 253 The interface described herein has not been prototyped or tested, and is presented only as an exam- ple of how such an interface might be achieved. As more development is done to verify the interface, this application note will be updated as appropriate. EPSON APPLICATION NOTES (S19A-G-005-05) 5-35...
Page 254: Interfacing To The Motorola Mmcf5307 Microprocessor
Figure 5-1 illustrates a typical memory read cycle on the MCF5307 system bus, and Figure 5-2 illus- trates a memory write cycle. BCLK0 A[31:0] SIZ[1:0], TT[1:0] D[31:0] Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 5-1 MCF5307 Memory Read Cycle EPSON 5-36 APPLICATION NOTES (S19A-G-005-05)
Page 255: Chip-Select Module
These chip selects are well-suited to typical I/O addressing requirements. Each chip select may be individually programmed for port size (8/16/32 bits), 0-15 wait states or external acknowledge, address space type, burst or non-burst cycle support, and write protect. EPSON APPLICATION NOTES (S19A-G-005-05) 5-37...
Page 256: S1D13504 Bus Interface
REG[1Bh] clears this bit to 0. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging. EPSON 5-38 APPLICATION NOTES (S19A-G-005-05)
Page 257: Generic Bus Interface Mode
MD5 at reset. • The Bus Status (BS#) signal is unused in general purpose bus mode, and should be tied high (con- nected to IO V EPSON APPLICATION NOTES (S19A-G-005-05) 5-39...
Page 258: Mcf5307 To S1D13504 Interface
Figure 5-3 shows a block diagram of the interface. MCF5307 S1D13504 M/R# A[20:0] AB[20:0] D[31:15] SD[15:0] 74AC08 (or equivalent) 470 pull-up WAIT# WE1# WE0# RD1# RD0# BCLK0 BUSCLK RESET RESET# Figure 5-3 Block Diagram of MCF5307 to S1D13504 Interface EPSON 5-40 APPLICATION NOTES (S19A-G-005-05)
Page 259: S1D13504 Hardware Configuration
Generic bus interface (e.g. MCF5307, ISA bus interface) Reserved = required settings for MCF5307 support. Table 5-3 Memory Conﬁguration Option Memory Selection Symmetrical 256K x 16 DRAM Symmetrical 1M x 16 DRAM Asymmetrical 256K x 16 DRAM Asymmetrical 1M x 16 DRAM EPSON APPLICATION NOTES (S19A-G-005-05) 5-41...
Page 260: Mcf5307 Chip Select Configuration
• PS (1:0) = 1:0 – memory port size is 16 bits • BEM = 0 – Byte enable/write enable active on writes only • BSTR = 0 – disable burst reads • BSTW = 0 – disable burst writes EPSON 5-42 APPLICATION NOTES (S19A-G-005-05)
Page 261: References
• “S5U13504P00C Rev. 1.0 ISA Bus Evaluation Board User’s Manual”; Document Number S19A- G-004-xx • “S1D13504 Programming Notes and Examples”; Document Number S19A-G-002-xx 5.5.2 Document Sources • Motorola Inc.: Motorola Literature Distribution Center, (800) 441-2447. • EPSON Research and Development web page: www.erd.epson.com EPSON APPLICATION NOTES (S19A-G-005-05) 5-43...
Page 262: Interfacing To The Toshiba Mips Tx3912 Processor
• System design using one ITE8368E PC Card/GPIO buffer chip (see Section 1.3.1, “Hardware Description—Using One IT8368E” on page 4). • System design using two ITE8368E PC Card/GPIO buffer chips (see Section 1.3.2, “Hardware Description—Using Two IT8368E’s” on page 5). EPSON 5-44 APPLICATION NOTES (S19A-G-005-05)
Page 263: Direct Connection To The Toshiba Tx3912
DCLKOUT (divided) as the clock source, should be based on the desired: • pixel and frame rates. • power budget. • part count. • maximum S1D13504 clock frequencies. The S1D13504 also has internal clock dividers providing additional ﬂexibility. EPSON APPLICATION NOTES (S19A-G-005-05) 5-45...
Page 264: Memory Mapping And Aliasing
When the S1D13504 is conﬁgured for Generic MPU host bus interface, the host interface pins are mapped as in the table below. Table 6-2 S1D13504 Generic MPU Host Bus Interface Pin Mapping Pin Name Pin Function WE1# WE1# Connect to IO V RD/WR# RD1# RD0# WE0# WE0# EPSON 5-46 APPLICATION NOTES (S19A-G-005-05)
Page 265: System Design Using The It8368E Pc Card Buffer
S1D13504 virtually transparent to PC Card devices that use the same slot. 6.3.1 Hardware Description—Using One IT8368E The ITE IT8368E has been speciﬁcally designed to support EPSON CRT/LCD controllers. The IT8368E provides eleven Multi-Function IO pins (MFIO). Conﬁguration registers can be used to allow these MFIO pins to provide the control signals required to implement the S1D13504 CPU interface.
Page 266: Hardware Description-Using Two It8368E's
DCLKOUT (divided) as the clock source, should be based on the desired: • pixel and frame rates. • power budget. • part count. • maximum S1D13504 clock frequencies. The S1D13504 also has internal clock dividers providing additional ﬂexibility. EPSON 5-48 APPLICATION NOTES (S19A-G-005-05)
Page 267: It8368E Configuration
131,072 times at 64 byte intervals S1D13504 display buffer, 0D80 0000h 8M byte aliased 4 times at 2M byte intervals 0E00 0000h 32M byte Card 2 Attribute 6800 0000h 64M byte Card 2 Memory EPSON APPLICATION NOTES (S19A-G-005-05) 5-49...
Page 268: S1D13504 Configuration
When the S1D13504 is conﬁgured for Generic MPU host bus interface, the host interface pins are mapped as in the table below. Table 6-6 S1D13504 Generic MPU Host Bus Interface Pin Mapping Pin Name Pin Function WE1# WE1# Connect to IO V RD/WR# RD1# RD0# WE0# WE0# EPSON 5-50 APPLICATION NOTES (S19A-G-005-05)
Page 269: Software
The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The S1D13504 test utilities and Windows CE v2.0 display drivers are available from your sales sup- port contact or www.erd.epson.com. EPSON APPLICATION NOTES (S19A-G-005-05)
Page 270: Power Consumption
An inactive bus (e.g. BUSCLK = low, Addr = low etc.) reduces overall system power consumption. • CLKI state during SUSPEND: disabling the CLKI during SUSPEND has substantial power sav- ings. EPSON 5-52 APPLICATION NOTES (S19A-G-005-05)
Page 271: Conditions
LCD frame-rate, whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state. In a typical design environment, the S1D13504 can be conﬁgured to be an extremely power-efﬁcient LCD Controller with high performance and ﬂexibility. EPSON APPLICATION NOTES (S19A-G-005-05) 5-53...
Page 272 Telex: 65542 EPSCO HX Crystal Lake, IL 60014, U.S.A. Phone: +1-815-455-7630 Fax: +1-815-455-7633 Northeast EPSON TAIWAN TECHNOLOGY & TRADING LTD. 301 Edgewater Place, Suite 120 10F, No. 287, Nanking East Road, Sec. 3 Wakefield, MA 01880, U.S.A. Taipei Phone: +1-781-246-3600...
Page 273 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
Page 274 S1D13504 Series Technicl Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue September,1998 This manual was made with recycle papaer, Printed April, 2001 in Japan and printed using soy-based inks.

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