Xilinx VCU118 User Manual page 27

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Table 3-3: DDR4 Memory 80-bit I/F C2 to FPGA U1 Banks 40, 41, and 42 (Cont'd)
FPGA (U1)
Schematic Net Name
Pin
AW31
DDR4_C2_DQ12
AW32
DDR4_C2_DQ13
AY32
DDR4_C2_DQ14
AY33
DDR4_C2_DQ15
BF30
DDR4_C2_DQS0_T
BF31
DDR4_C2_DQS0_C
AY34
DDR4_C2_DQS1_T
BA34
DDR4_C2_DQS1_C
BE32
DDR4_C2_DM0
BB31
DDR4_C2_DM1
AV30
DDR4_C2_DQ16
AW30
DDR4_C2_DQ17
AU33
DDR4_C2_DQ18
AU34
DDR4_C2_DQ19
AT31
DDR4_C2_DQ20
AU32
DDR4_C2_DQ21
AU31
DDR4_C2_DQ22
AV31
DDR4_C2_DQ23
AR33
DDR4_C2_DQ24
AT34
DDR4_C2_DQ25
AT29
DDR4_C2_DQ26
AT30
DDR4_C2_DQ27
AP30
DDR4_C2_DQ28
AR30
DDR4_C2_DQ29
AN30
DDR4_C2_DQ30
AN31
DDR4_C2_DQ31
AU29
DDR4_C2_DQS2_T
AV29
DDR4_C2_DQS2_C
AP31
DDR4_C2_DQS3_T
AP32
DDR4_C2_DQS3_C
AV33
DDR4_C2_DM2
AR32
DDR4_C2_DM3
BE34
DDR4_C2_DQ32
BF34
DDR4_C2_DQ33
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Standard
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
www.xilinx.com
Chapter 3: Board Component Descriptions
Component Memory
Pin #
Pin Name
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
G3
DQSL_T
F3
DQSL_C
B7
DQSU_T
A7
DQSU_C
E7
DML_B/DBIL_B
E2
DMU_B/DBIU_B
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
G3
DQSL_C
F3
DQSL_T
B7
DQSU_C
A7
DQSU_T
E7
DML_B/DBIL_B
E2
DMU_B/DBIU_B
G2
DQL0
F7
DQL1
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Ref. Des.
U135
U135
U135
U135
U135
U135
U135
U135
U135
U135
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U136
U137
U137
27

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