Xilinx VCU118 User Manual page 117

set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
LVDS [get_ports "CLK_125MHZ_N"];
AL20 [get_ports "FPGA_EMCCLK"];
LVCMOS18 [get_ports "FPGA_EMCCLK"];
R32 [get_ports "USER_SMA_CLOCK_P"];
LVDS [get_ports "USER_SMA_CLOCK_P"];
P32 [get_ports "USER_SMA_CLOCK_N"];
LVDS [get_ports "USER_SMA_CLOCK_N"];
E12 [get_ports "250MHZ_CLK1_P"];
LVDS [get_ports "250MHZ_CLK1_P"];
D12 [get_ports "250MHZ_CLK1_N"];
LVDS [get_ports "250MHZ_CLK1_N"];
AW26 [get_ports "250MHZ_CLK2_P"];
LVDS [get_ports "250MHZ_CLK2_P"];
AW27 [get_ports "250MHZ_CLK2_N"];
LVDS [get_ports "250MHZ_CLK2_N"];
AM23 [get_ports "QSFP1_RECCLK_P"];
LVDS [get_ports "QSFP1_RECCLK_P"];
AM22 [get_ports "QSFP1_RECCLK_N"];
LVDS [get_ports "QSFP1_RECCLK_N"];
AP23 [get_ports "QSFP2_RECCLK_P"];
LVDS [get_ports "QSFP2_RECCLK_P"];
AP22 [get_ports "QSFP2_RECCLK_N"];
LVDS [get_ports "QSFP2_RECCLK_N"];
H32 [get_ports "USER_SI570_CLOCK_P "];
LVDS [get_ports "USER_SI570_CLOCK_P"];
G32 [get_ports "USER_SI570_CLOCK_N "];
LVDS [get_ports "USER_SI570_CLOCK_N"];
AW23 [get_ports "USER_SI570_CLOCK1_P"];
LVDS [get_ports "USER_SI570_CLOCK1_P"];
AW22 [get_ports "USER_SI570_CLOCK1_N"];
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