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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
POD12_DCI
[get_ports "DDR4_C1_DQ70"];
A21
[get_ports "DDR4_C1_DQ71"];
POD12_DCI
[get_ports "DDR4_C1_DQ71"];
D7
[get_ports "DDR4_C1_DQ72"];
POD12_DCI
[get_ports "DDR4_C1_DQ72"];
C7
[get_ports "DDR4_C1_DQ73"];
POD12_DCI
[get_ports "DDR4_C1_DQ73"];
B8
[get_ports "DDR4_C1_DQ74"];
POD12_DCI
[get_ports "DDR4_C1_DQ74"];
B7
[get_ports "DDR4_C1_DQ75"];
POD12_DCI
[get_ports "DDR4_C1_DQ75"];
C10
[get_ports "DDR4_C1_DQ76"];
POD12_DCI
[get_ports "DDR4_C1_DQ76"];
B10
[get_ports "DDR4_C1_DQ77"];
POD12_DCI
[get_ports "DDR4_C1_DQ77"];
B11
[get_ports "DDR4_C1_DQ78"];
POD12_DCI
[get_ports "DDR4_C1_DQ78"];
A11
[get_ports "DDR4_C1_DQ79"];
POD12_DCI
[get_ports "DDR4_C1_DQ79"];
D14
[get_ports "DDR4_C1_A0 "];
SSTL12_DCI
[get_ports "DDR4_C1_A0 "];
B15
[get_ports "DDR4_C1_A1 "];
SSTL12_DCI
[get_ports "DDR4_C1_A1 "];
B16
[get_ports "DDR4_C1_A2 "];
SSTL12_DCI
[get_ports "DDR4_C1_A2 "];
C14
[get_ports "DDR4_C1_A3 "];
SSTL12_DCI
[get_ports "DDR4_C1_A3 "];
C15
[get_ports "DDR4_C1_A4 "];
SSTL12_DCI
[get_ports "DDR4_C1_A4 "];
A13
[get_ports "DDR4_C1_A5 "];
SSTL12_DCI
[get_ports "DDR4_C1_A5 "];
A14
[get_ports "DDR4_C1_A6 "];
SSTL12_DCI
[get_ports "DDR4_C1_A6 "];
A15
[get_ports "DDR4_C1_A7 "];
SSTL12_DCI
[get_ports "DDR4_C1_A7 "];
A16
[get_ports "DDR4_C1_A8 "];
SSTL12_DCI
[get_ports "DDR4_C1_A8 "];
B12
[get_ports "DDR4_C1_A9 "];
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