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set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
AL27
[get_ports "DDR4_C2_A1 "];
SSTL12_DCI
[get_ports "DDR4_C2_A1 "];
AP26
[get_ports "DDR4_C2_A2 "];
SSTL12_DCI
[get_ports "DDR4_C2_A2 "];
AP25
[get_ports "DDR4_C2_A3 "];
SSTL12_DCI
[get_ports "DDR4_C2_A3 "];
AN28
[get_ports "DDR4_C2_A4 "];
SSTL12_DCI
[get_ports "DDR4_C2_A4 "];
AM28
[get_ports "DDR4_C2_A5 "];
SSTL12_DCI
[get_ports "DDR4_C2_A5 "];
AP28
[get_ports "DDR4_C2_A6 "];
SSTL12_DCI
[get_ports "DDR4_C2_A6 "];
AP27
[get_ports "DDR4_C2_A7 "];
SSTL12_DCI
[get_ports "DDR4_C2_A7 "];
AN26
[get_ports "DDR4_C2_A8 "];
SSTL12_DCI
[get_ports "DDR4_C2_A8 "];
AM26
[get_ports "DDR4_C2_A9 "];
SSTL12_DCI
[get_ports "DDR4_C2_A9 "];
AR28
[get_ports "DDR4_C2_A10"];
SSTL12_DCI
[get_ports "DDR4_C2_A10"];
AR27
[get_ports "DDR4_C2_A11"];
SSTL12_DCI
[get_ports "DDR4_C2_A11"];
AV25
[get_ports "DDR4_C2_A12"];
SSTL12_DCI
[get_ports "DDR4_C2_A12"];
AT25
[get_ports "DDR4_C2_A13"];
SSTL12_DCI
[get_ports "DDR4_C2_A13"];
AV28
[get_ports "DDR4_C2_A14_WE_B"];
SSTL12_DCI
[get_ports "DDR4_C2_A14_WE_B"];
AU26
[get_ports "DDR4_C2_A15_CAS_B"];
SSTL12_DCI
[get_ports "DDR4_C2_A15_CAS_B"];
AV26
[get_ports "DDR4_C2_A16_RAS_B"];
SSTL12_DCI
[get_ports "DDR4_C2_A16_RAS_B"];
AR25
[get_ports "DDR4_C2_BA0"];
SSTL12_DCI
[get_ports "DDR4_C2_BA0"];
AU28
[get_ports "DDR4_C2_BA1"];
SSTL12_DCI
[get_ports "DDR4_C2_BA1"];
AU27
[get_ports "DDR4_C2_BG0"];
SSTL12_DCI
[get_ports "DDR4_C2_BG0"];
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