Xilinx VCU118 User Manual page 135

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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
SSTL12
[get_ports "RLD3_C3_72B_DQ34"];
A34
[get_ports "RLD3_C3_72B_DQ35"];
SSTL12
[get_ports "RLD3_C3_72B_DQ35"];
T24
[get_ports "RLD3_C3_72B_DQ36"];
SSTL12
[get_ports "RLD3_C3_72B_DQ36"];
R24
[get_ports "RLD3_C3_72B_DQ37"];
SSTL12
[get_ports "RLD3_C3_72B_DQ37"];
R27
[get_ports "RLD3_C3_72B_DQ38"];
SSTL12
[get_ports "RLD3_C3_72B_DQ38"];
P27
[get_ports "RLD3_C3_72B_DQ39"];
SSTL12
[get_ports "RLD3_C3_72B_DQ39"];
P25
[get_ports "RLD3_C3_72B_DQ40"];
SSTL12
[get_ports "RLD3_C3_72B_DQ40"];
N25
[get_ports "RLD3_C3_72B_DQ41"];
SSTL12
[get_ports "RLD3_C3_72B_DQ41"];
P26
[get_ports "RLD3_C3_72B_DQ42"];
SSTL12
[get_ports "RLD3_C3_72B_DQ42"];
N27
[get_ports "RLD3_C3_72B_DQ43"];
SSTL12
[get_ports "RLD3_C3_72B_DQ43"];
P24
[get_ports "RLD3_C3_72B_DQ44"];
SSTL12
[get_ports "RLD3_C3_72B_DQ44"];
M25
[get_ports "RLD3_C3_72B_DQ45"];
SSTL12
[get_ports "RLD3_C3_72B_DQ45"];
L26
[get_ports "RLD3_C3_72B_DQ46"];
SSTL12
[get_ports "RLD3_C3_72B_DQ46"];
L28
[get_ports "RLD3_C3_72B_DQ47"];
SSTL12
[get_ports "RLD3_C3_72B_DQ47"];
K28
[get_ports "RLD3_C3_72B_DQ48"];
SSTL12
[get_ports "RLD3_C3_72B_DQ48"];
L24
[get_ports "RLD3_C3_72B_DQ49"];
SSTL12
[get_ports "RLD3_C3_72B_DQ49"];
L25
[get_ports "RLD3_C3_72B_DQ50"];
SSTL12
[get_ports "RLD3_C3_72B_DQ50"];
K26
[get_ports "RLD3_C3_72B_DQ51"];
SSTL12
[get_ports "RLD3_C3_72B_DQ51"];
J26
[get_ports "RLD3_C3_72B_DQ52"];
SSTL12
[get_ports "RLD3_C3_72B_DQ52"];
K27
[get_ports "RLD3_C3_72B_DQ53"];
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