Xilinx VCU118 User Manual page 137

set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
SSTL12 [get_ports "RLD3_C3_72B_A0"];
C29 [get_ports "RLD3_C3_72B_A1"];
SSTL12 [get_ports "RLD3_C3_72B_A1"];
D29 [get_ports "RLD3_C3_72B_A2"];
SSTL12 [get_ports "RLD3_C3_72B_A2"];
B30 [get_ports "RLD3_C3_72B_A3"];
SSTL12 [get_ports "RLD3_C3_72B_A3"];
C30 [get_ports "RLD3_C3_72B_A4"];
SSTL12 [get_ports "RLD3_C3_72B_A4"];
A31 [get_ports "RLD3_C3_72B_A5"];
SSTL12 [get_ports "RLD3_C3_72B_A5"];
A30 [get_ports "RLD3_C3_72B_A6"];
SSTL12 [get_ports "RLD3_C3_72B_A6"];
A33 [get_ports "RLD3_C3_72B_A7"];
SSTL12 [get_ports "RLD3_C3_72B_A7"];
B33 [get_ports "RLD3_C3_72B_A8"];
SSTL12 [get_ports "RLD3_C3_72B_A8"];
B32 [get_ports "RLD3_C3_72B_A9"];
SSTL12 [get_ports "RLD3_C3_72B_A9"];
B31 [get_ports "RLD3_C3_72B_A10"];
SSTL12 [get_ports "RLD3_C3_72B_A10"];
C33 [get_ports "RLD3_C3_72B_A11"];
SSTL12 [get_ports "RLD3_C3_72B_A11"];
C32 [get_ports "RLD3_C3_72B_A12"];
SSTL12 [get_ports "RLD3_C3_72B_A12"];
D30 [get_ports "RLD3_C3_72B_A13"];
SSTL12 [get_ports "RLD3_C3_72B_A13"];
E29 [get_ports "RLD3_C3_72B_A14"];
SSTL12 [get_ports "RLD3_C3_72B_A14"];
F29 [get_ports "RLD3_C3_72B_A15"];
SSTL12 [get_ports "RLD3_C3_72B_A15"];
D32 [get_ports "RLD3_C3_72B_A16"];
SSTL12 [get_ports "RLD3_C3_72B_A16"];
E32 [get_ports "RLD3_C3_72B_A17"];
SSTL12 [get_ports "RLD3_C3_72B_A17"];
D31 [get_ports "RLD3_C3_72B_A18"];
SSTL12 [get_ports "RLD3_C3_72B_A18"];
E31 [get_ports "RLD3_C3_72B_A19"];
www.xilinx.com
137
Send Feedback