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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
SSTL12_DCI
[get_ports "DDR4_C1_A9 "];
C12
[get_ports "DDR4_C1_A10"];
SSTL12_DCI
[get_ports "DDR4_C1_A10"];
B13
[get_ports "DDR4_C1_A11"];
SSTL12_DCI
[get_ports "DDR4_C1_A11"];
C13
[get_ports "DDR4_C1_A12"];
SSTL12_DCI
[get_ports "DDR4_C1_A12"];
D15
[get_ports "DDR4_C1_A13"];
SSTL12_DCI
[get_ports "DDR4_C1_A13"];
H14
[get_ports "DDR4_C1_A14_WE_B"];
SSTL12_DCI
[get_ports "DDR4_C1_A14_WE_B"];
H15
[get_ports "DDR4_C1_A15_CAS_B"];
SSTL12_DCI
[get_ports "DDR4_C1_A15_CAS_B"];
F15
[get_ports "DDR4_C1_A16_RAS_B"];
SSTL12_DCI
[get_ports "DDR4_C1_A16_RAS_B"];
G15
[get_ports "DDR4_C1_BA0"];
SSTL12_DCI
[get_ports "DDR4_C1_BA0"];
G13
[get_ports "DDR4_C1_BA1"];
SSTL12_DCI
[get_ports "DDR4_C1_BA1"];
H13
[get_ports "DDR4_C1_BG0"];
SSTL12_DCI
[get_ports "DDR4_C1_BG0"];
G11
[get_ports "DDR4_C1_DM0"];
POD12_DCI
[get_ports "DDR4_C1_DM0"];
R18
[get_ports "DDR4_C1_DM1"];
POD12_DCI
[get_ports "DDR4_C1_DM1"];
K17
[get_ports "DDR4_C1_DM2"];
POD12_DCI
[get_ports "DDR4_C1_DM2"];
G18
[get_ports "DDR4_C1_DM3"];
POD12_DCI
[get_ports "DDR4_C1_DM3"];
B18
[get_ports "DDR4_C1_DM4"];
POD12_DCI
[get_ports "DDR4_C1_DM4"];
P20
[get_ports "DDR4_C1_DM5"];
POD12_DCI
[get_ports "DDR4_C1_DM5"];
L23
[get_ports "DDR4_C1_DM6"];
POD12_DCI
[get_ports "DDR4_C1_DM6"];
G22
[get_ports "DDR4_C1_DM7"];
POD12_DCI
[get_ports "DDR4_C1_DM7"];
E24
[get_ports "DDR4_C1_DM8"];
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