Xilinx VCU118 User Manual page 140

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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
# BPI FLASH
# BPI_FLASH_D[3:0] are wired to FPGA U1 Bank 0
# CONFIGURATION BITS D[3:0} ARE NOT USER ACCESSIBLE
# PACKAGE_PIN AP11 - BPI_FLASH_D0 Bank 0 - D00_MOSI_0
# PACKAGE_PIN AN11 - BPI_FLASH_D1 Bank 0 - D01_DIN_0
# PACKAGE_PIN AM11 - BPI_FLASH_D2 Bank 0 - D02_0
# PACKAGE_PIN AL11 - BPI_FLASH_D3 Bank 0 - D03_0
# PACKAGE_PIN AJ11 - BPI_FLASH_CE_B Bank 0 - RDWR_FCS_B_0
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
SSTL12
[get_ports "RLD3_C3_72B_CK_P"];
H30
[get_ports "RLD3_C3_72B_CK_N"];
SSTL12
[get_ports "RLD3_C3_72B_CK_N"];
K29
[get_ports "RLD3_C3_72B_WE_B"];
SSTL12
[get_ports "RLD3_C3_72B_WE_B"];
L30
[get_ports "RLD3_C3_72B_REF_B"];
SSTL12
[get_ports "RLD3_C3_72B_REF_B"];
N29
[get_ports "RLD3_C3_72B_CS_B"];
SSTL12
[get_ports "RLD3_C3_72B_CS_B"];
L29
[get_ports "RLD3_C3_72B_RESET_B"];
SSTL12
[get_ports "RLD3_C3_72B_RESET_B"];
AM19
[get_ports "BPI_FLASH_D4"];
LVCMOS18
[get_ports "BPI_FLASH_D4"];
AM18
[get_ports "BPI_FLASH_D5"];
LVCMOS18
[get_ports "BPI_FLASH_D5"];
AN20
[get_ports "BPI_FLASH_D6"];
LVCMOS18
[get_ports "BPI_FLASH_D6"];
AP20
[get_ports "BPI_FLASH_D7"];
LVCMOS18
[get_ports "BPI_FLASH_D7"];
AN19
[get_ports "BPI_FLASH_D8"];
LVCMOS18
[get_ports "BPI_FLASH_D8"];
AN18
[get_ports "BPI_FLASH_D9"];
LVCMOS18
[get_ports "BPI_FLASH_D9"];
AR18
[get_ports "BPI_FLASH_D10"];
LVCMOS18
[get_ports "BPI_FLASH_D10"];
AR17
[get_ports "BPI_FLASH_D11"];
LVCMOS18
[get_ports "BPI_FLASH_D11"];
AT20
[get_ports "BPI_FLASH_D12"];
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