Xilinx VCU118 User Manual page 126

set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
BD33 [get_ports "DDR4_C2_DQ5"];
POD12_DCI [get_ports "DDR4_C2_DQ5"];
BC31 [get_ports "DDR4_C2_DQ6"];
POD12_DCI [get_ports "DDR4_C2_DQ6"];
BD31 [get_ports "DDR4_C2_DQ7"];
POD12_DCI [get_ports "DDR4_C2_DQ7"];
BA32 [get_ports "DDR4_C2_DQ8"];
POD12_DCI [get_ports "DDR4_C2_DQ8"];
BB33 [get_ports "DDR4_C2_DQ9"];
POD12_DCI [get_ports "DDR4_C2_DQ9"];
BA30 [get_ports "DDR4_C2_DQ10"];
POD12_DCI [get_ports "DDR4_C2_DQ10"];
BA31 [get_ports "DDR4_C2_DQ11"];
POD12_DCI [get_ports "DDR4_C2_DQ11"];
AW31 [get_ports "DDR4_C2_DQ12"];
POD12_DCI [get_ports "DDR4_C2_DQ12"];
AW32 [get_ports "DDR4_C2_DQ13"];
POD12_DCI [get_ports "DDR4_C2_DQ13"];
AY32 [get_ports "DDR4_C2_DQ14"];
POD12_DCI [get_ports "DDR4_C2_DQ14"];
AY33 [get_ports "DDR4_C2_DQ15"];
POD12_DCI [get_ports "DDR4_C2_DQ15"];
AV30 [get_ports "DDR4_C2_DQ16"];
POD12_DCI [get_ports "DDR4_C2_DQ16"];
AW30 [get_ports "DDR4_C2_DQ17"];
POD12_DCI [get_ports "DDR4_C2_DQ17"];
AU33 [get_ports "DDR4_C2_DQ18"];
POD12_DCI [get_ports "DDR4_C2_DQ18"];
AU34 [get_ports "DDR4_C2_DQ19"];
POD12_DCI [get_ports "DDR4_C2_DQ19"];
AT31 [get_ports "DDR4_C2_DQ20"];
POD12_DCI [get_ports "DDR4_C2_DQ20"];
AU32 [get_ports "DDR4_C2_DQ21"];
POD12_DCI [get_ports "DDR4_C2_DQ21"];
AU31 [get_ports "DDR4_C2_DQ22"];
POD12_DCI [get_ports "DDR4_C2_DQ22"];
AV31 [get_ports "DDR4_C2_DQ23"];
POD12_DCI [get_ports "DDR4_C2_DQ23"];
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