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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
POD12_DCI
[get_ports "DDR4_C1_DQ32"];
C17
[get_ports "DDR4_C1_DQ33"];
POD12_DCI
[get_ports "DDR4_C1_DQ33"];
C19
[get_ports "DDR4_C1_DQ34"];
POD12_DCI
[get_ports "DDR4_C1_DQ34"];
C18
[get_ports "DDR4_C1_DQ35"];
POD12_DCI
[get_ports "DDR4_C1_DQ35"];
D20
[get_ports "DDR4_C1_DQ36"];
POD12_DCI
[get_ports "DDR4_C1_DQ36"];
D19
[get_ports "DDR4_C1_DQ37"];
POD12_DCI
[get_ports "DDR4_C1_DQ37"];
C20
[get_ports "DDR4_C1_DQ38"];
POD12_DCI
[get_ports "DDR4_C1_DQ38"];
B20
[get_ports "DDR4_C1_DQ39"];
POD12_DCI
[get_ports "DDR4_C1_DQ39"];
N23
[get_ports "DDR4_C1_DQ40"];
POD12_DCI
[get_ports "DDR4_C1_DQ40"];
M23
[get_ports "DDR4_C1_DQ41"];
POD12_DCI
[get_ports "DDR4_C1_DQ41"];
R21
[get_ports "DDR4_C1_DQ42"];
POD12_DCI
[get_ports "DDR4_C1_DQ42"];
P21
[get_ports "DDR4_C1_DQ43"];
POD12_DCI
[get_ports "DDR4_C1_DQ43"];
R22
[get_ports "DDR4_C1_DQ44"];
POD12_DCI
[get_ports "DDR4_C1_DQ44"];
P22
[get_ports "DDR4_C1_DQ45"];
POD12_DCI
[get_ports "DDR4_C1_DQ45"];
T23
[get_ports "DDR4_C1_DQ46"];
POD12_DCI
[get_ports "DDR4_C1_DQ46"];
R23
[get_ports "DDR4_C1_DQ47"];
POD12_DCI
[get_ports "DDR4_C1_DQ47"];
K24
[get_ports "DDR4_C1_DQ48"];
POD12_DCI
[get_ports "DDR4_C1_DQ48"];
J24
[get_ports "DDR4_C1_DQ49"];
POD12_DCI
[get_ports "DDR4_C1_DQ49"];
M21
[get_ports "DDR4_C1_DQ50"];
POD12_DCI
[get_ports "DDR4_C1_DQ50"];
L21
[get_ports "DDR4_C1_DQ51"];
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