Xilinx VCU118 User Manual page 156

#USB UART
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
# SYSMON
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
# GPIO DIP SWITCH
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
# GPIO LEDs
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
BB22 [get_ports "USB_UART_CTS"];
LVCMOS18 [get_ports "USB_UART_CTS"];
AY25 [get_ports "USB_UART_RTS"];
LVCMOS18 [get_ports "USB_UART_RTS"];
BB21 [get_ports "USB_UART_RX"];
LVCMOS18 [get_ports "USB_UART_RX"];
AW25 [get_ports "USB_UART_TX"];
LVCMOS18 [get_ports "USB_UART_TX"];
AP18 [get_ports "SYSMON_SCL "];
LVCMOS18 [get_ports "SYSMON_SCL "];
AP17 [get_ports "SYSMON_SDA "];
LVCMOS18 [get_ports "SYSMON_SDA "];
B17 [get_ports "GPIO_DIP_SW1"];
LVCMOS12 [get_ports "GPIO_DIP_SW1"];
G16 [get_ports "GPIO_DIP_SW2"];
LVCMOS12 [get_ports "GPIO_DIP_SW2"];
J16 [get_ports "GPIO_DIP_SW3"];
LVCMOS12 [get_ports "GPIO_DIP_SW3"];
D21 [get_ports "GPIO_DIP_SW4"];
LVCMOS12 [get_ports "GPIO_DIP_SW4"];
AT32 [get_ports "GPIO_LED0"];
LVCMOS12 [get_ports "GPIO_LED0"];
AV34 [get_ports "GPIO_LED1"];
LVCMOS12 [get_ports "GPIO_LED1"];
AY30 [get_ports "GPIO_LED2"];
LVCMOS12 [get_ports "GPIO_LED2"];
BB32 [get_ports "GPIO_LED3"];
LVCMOS12 [get_ports "GPIO_LED3"];
BF32 [get_ports "GPIO_LED4"];
LVCMOS12 [get_ports "GPIO_LED4"];
AU37 [get_ports "GPIO_LED5"];
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