Xilinx VCU118 User Manual page 128

set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
BD40 [get_ports "DDR4_C2_DQ43"];
POD12_DCI [get_ports "DDR4_C2_DQ43"];
BB38 [get_ports "DDR4_C2_DQ44"];
POD12_DCI [get_ports "DDR4_C2_DQ44"];
BB39 [get_ports "DDR4_C2_DQ45"];
POD12_DCI [get_ports "DDR4_C2_DQ45"];
BC38 [get_ports "DDR4_C2_DQ46"];
POD12_DCI [get_ports "DDR4_C2_DQ46"];
BD38 [get_ports "DDR4_C2_DQ47"];
POD12_DCI [get_ports "DDR4_C2_DQ47"];
BB36 [get_ports "DDR4_C2_DQ48"];
POD12_DCI [get_ports "DDR4_C2_DQ48"];
BB37 [get_ports "DDR4_C2_DQ49"];
POD12_DCI [get_ports "DDR4_C2_DQ49"];
BA39 [get_ports "DDR4_C2_DQ50"];
POD12_DCI [get_ports "DDR4_C2_DQ50"];
BA40 [get_ports "DDR4_C2_DQ51"];
POD12_DCI [get_ports "DDR4_C2_DQ51"];
AW40 [get_ports "DDR4_C2_DQ52"];
POD12_DCI [get_ports "DDR4_C2_DQ52"];
AY40 [get_ports "DDR4_C2_DQ53"];
POD12_DCI [get_ports "DDR4_C2_DQ53"];
AY38 [get_ports "DDR4_C2_DQ54"];
POD12_DCI [get_ports "DDR4_C2_DQ54"];
AY39 [get_ports "DDR4_C2_DQ55"];
POD12_DCI [get_ports "DDR4_C2_DQ55"];
AW35 [get_ports "DDR4_C2_DQ56"];
POD12_DCI [get_ports "DDR4_C2_DQ56"];
AW36 [get_ports "DDR4_C2_DQ57"];
POD12_DCI [get_ports "DDR4_C2_DQ57"];
AU40 [get_ports "DDR4_C2_DQ58"];
POD12_DCI [get_ports "DDR4_C2_DQ58"];
AV40 [get_ports "DDR4_C2_DQ59"];
POD12_DCI [get_ports "DDR4_C2_DQ59"];
AU38 [get_ports "DDR4_C2_DQ60"];
POD12_DCI [get_ports "DDR4_C2_DQ60"];
AU39 [get_ports "DDR4_C2_DQ61"];
POD12_DCI [get_ports "DDR4_C2_DQ61"];
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