Xilinx VCU118 User Manual page 138

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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
SSTL12
[get_ports "RLD3_C3_72B_A19"];
R28
[get_ports "RLD3_C3_72B_A20"];
SSTL12
[get_ports "RLD3_C3_72B_A20"];
E33
[get_ports "RLD3_C3_72B_BA0"];
SSTL12
[get_ports "RLD3_C3_72B_BA0"];
F33
[get_ports "RLD3_C3_72B_BA1"];
SSTL12
[get_ports "RLD3_C3_72B_BA1"];
F30
[get_ports "RLD3_C3_72B_BA2"];
SSTL12
[get_ports "RLD3_C3_72B_BA2"];
G30
[get_ports "RLD3_C3_72B_BA3"];
SSTL12
[get_ports "RLD3_C3_72B_BA3"];
F39
[get_ports "RLD3_C3_72B_DM0"];
SSTL12
[get_ports "RLD3_C3_72B_DM0"];
A35
[get_ports "RLD3_C3_72B_DM1"];
SSTL12
[get_ports "RLD3_C3_72B_DM1"];
N24
[get_ports "RLD3_C3_72B_DM2"];
SSTL12
[get_ports "RLD3_C3_72B_DM2"];
B25
[get_ports "RLD3_C3_72B_DM3"];
SSTL12
[get_ports "RLD3_C3_72B_DM3"];
J31
[get_ports "RLD3_C3_72B_DK0_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_DK0_N"];
K31
[get_ports "RLD3_C3_72B_DK0_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_DK0_P"];
J32
[get_ports "RLD3_C3_72B_DK1_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_DK1_N"];
K32
[get_ports "RLD3_C3_72B_DK1_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_DK1_P"];
J30
[get_ports "RLD3_C3_72B_DK2_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_DK2_N"];
J29
[get_ports "RLD3_C3_72B_DK2_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_DK2_P"];
G33
[get_ports "RLD3_C3_72B_DK3_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_DK3_N"];
H33
[get_ports "RLD3_C3_72B_DK3_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_DK3_P"];
J40
[get_ports "RLD3_C3_72B_QK0_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK0_N"];
J39
[get_ports "RLD3_C3_72B_QK0_P"];
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