Xilinx VCU118 User Manual page 32

Table 3-4: RLD3 Memory 72-bit I/F to FPGA U1 Banks 46, 47, and 48 (Cont'd)
FPGA
Schematic Net Name
(U1) Pin
A40 RLD3_C3_72B_DQ23
D40 RLD3_C3_72B_DQ24
C40 RLD3_C3_72B_DQ25
B38 RLD3_C3_72B_DQ26
D35 RLD3_C3_72B_DQ27
C35 RLD3_C3_72B_DQ28
D34 RLD3_C3_72B_DQ29
C34 RLD3_C3_72B_DQ30
B36 RLD3_C3_72B_DQ31
B37 RLD3_C3_72B_DQ32
B35 RLD3_C3_72B_DQ33
A36 RLD3_C3_72B_DQ34
A34 RLD3_C3_72B_DQ35
F39 RLD3_C3_72B_DM0
A35 RLD3_C3_72B_DM1
J39 RLD3_C3_72B_QK0_P
J40 RLD3_C3_72B_QK0_N
F34 RLD3_C3_72B_QK1_P
E34 RLD3_C3_72B_QK1_N
E39 RLD3_C3_72B_QK2_P
D39 RLD3_C3_72B_QK2_N
D37 RLD3_C3_72B_QK3_P
C37 RLD3_C3_72B_QK3_N
G37 RLD3_C3_72B_QVLD0
A38 RLD3_C3_72B_QVLD1
T24 RLD3_C3_72B_DQ36
R24 RLD3_C3_72B_DQ37
R27 RLD3_C3_72B_DQ38
P27 RLD3_C3_72B_DQ39
P25 RLD3_C3_72B_DQ40
N25 RLD3_C3_72B_DQ41
P26 RLD3_C3_72B_DQ42
N27 RLD3_C3_72B_DQ43
P24 RLD3_C3_72B_DQ44
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Standard
Pin #
SSTL12 B5
SSTL12 B3
SSTL12 A6
SSTL12 A4
SSTL12 J4
SSTL12 K3
SSTL12 K1
SSTL12 L6
SSTL12 L4
SSTL12 L2
SSTL12 M5
SSTL12 M3
SSTL12 N6
SSTL12 B7
SSTL12 M7
DIFF_SSTL12 D9
DIFF_SSTL12 E8
DIFF_SSTL12 K9
DIFF_SSTL12 J8
DIFF_SSTL12 D5
DIFF_SSTL12 E6
DIFF_SSTL12 K5
DIFF_SSTL12 J6
SSTL12 J12
SSTL12 J2
SSTL12 D11
SSTL12 E10
SSTL12 C8
SSTL12 C10
SSTL12 C12
SSTL12 B9
SSTL12 B11
SSTL12 A8
SSTL12 A10
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Chapter 3: Board Component Descriptions
Component Memory
Pin Name
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DM0
DM1
QK0
QK0_B
QK1
QK1_B
QK2
QK2_B
QK3
QK3_B
QVLD0
QVLD1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
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Ref. Des.
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U142
U142
U142
U142
U142
U142
U142
U142
U142
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