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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
POD12_DCI
[get_ports "DDR4_C1_DM8"];
C9
[get_ports "DDR4_C1_DM9"];
POD12_DCI
[get_ports "DDR4_C1_DM9"];
D10
[get_ports "DDR4_C1_DQS0_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS0_C"];
D11
[get_ports "DDR4_C1_DQS0_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS0_T"];
P16
[get_ports "DDR4_C1_DQS1_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS1_C"];
P17
[get_ports "DDR4_C1_DQS1_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS1_T"];
J19
[get_ports "DDR4_C1_DQS2_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS2_C"];
K19
[get_ports "DDR4_C1_DQS2_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS2_T"];
E16
[get_ports "DDR4_C1_DQS3_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS3_C"];
F16
[get_ports "DDR4_C1_DQS3_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS3_T"];
A18
[get_ports "DDR4_C1_DQS4_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS4_C"];
A19
[get_ports "DDR4_C1_DQS4_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS4_T"];
M22
[get_ports "DDR4_C1_DQS5_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS5_C"];
N22
[get_ports "DDR4_C1_DQS5_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS5_T"];
L20
[get_ports "DDR4_C1_DQS6_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS6_C"];
M20
[get_ports "DDR4_C1_DQS6_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS6_T"];
G23
[get_ports "DDR4_C1_DQS7_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS7_C"];
H24
[get_ports "DDR4_C1_DQS7_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS7_T"];
C22
[get_ports "DDR4_C1_DQS8_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS8_C"];
D22
[get_ports "DDR4_C1_DQS8_T"];
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