Xilinx VCU118 User Manual page 113

Figure 3-30 shows mode switch SW16.
X-Ref Target - Figure 3-30
The mode pins settings on SW16 determine if the linear BPI flash is used for configuring the
FPGA. DIP switch SW16 also includes a system controller enable switch in position 1.
To obtain the fastest configuration speed, an external 90 MHz clock from the Silicon Labs
Si5335A U122 is wired to the EMCCLK pin of the FPGA on bank 65 pin AL20. This allows the
creation of bitstreams to configure the FPGA over the 16-bit datapath from the linear BPI
flash memory at a maximum synchronous read rate of 90 MHz.
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Figure 3-30: SW16 Default Settings
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Chapter 3: Board Component Descriptions
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