Xilinx VCU118 User Manual page 34

Table 3-4: RLD3 Memory 72-bit I/F to FPGA U1 Banks 46, 47, and 48 (Cont'd)
FPGA
Schematic Net Name
(U1) Pin
F26 RLD3_C3_72B_QK6_N
D27 RLD3_C3_72B_QK7_P
C28 RLD3_C3_72B_QK7_N
J27 RLD3_C3_72B_QVLD2
F25 RLD3_C3_72B_QVLD3
A29 RLD3_C3_72B_A0
C29 RLD3_C3_72B_A1
D29 RLD3_C3_72B_A2
B30 RLD3_C3_72B_A3
C30 RLD3_C3_72B_A4
A31 RLD3_C3_72B_A5
A30 RLD3_C3_72B_A6
A33 RLD3_C3_72B_A7
B33 RLD3_C3_72B_A8
B32 RLD3_C3_72B_A9
B31 RLD3_C3_72B_A10
C33 RLD3_C3_72B_A11
C32 RLD3_C3_72B_A12
D30 RLD3_C3_72B_A13
E29 RLD3_C3_72B_A14
F29 RLD3_C3_72B_A15
D32 RLD3_C3_72B_A16
E32 RLD3_C3_72B_A17
D31 RLD3_C3_72B_A18
E31 RLD3_C3_72B_A19
R28 RLD3_C3_72B_A20
E33 RLD3_C3_72B_BA0
F33 RLD3_C3_72B_BA1
F30 RLD3_C3_72B_BA2
G30 RLD3_C3_72B_BA3
K29 RLD3_C3_72B_WE_B
L30 RLD3_C3_72B_REF_B
H29 RLD3_C3_72B_CK_P
H30 RLD3_C3_72B_CK_N
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Standard
Pin #
DIFF_SSTL12 E6
DIFF_SSTL12 K5
DIFF_SSTL12 J6
DIFF_SSTL12 J12
DIFF_SSTL12 J2
SSTL12 E2
SSTL12 F5
SSTL12 F4
SSTL12 F9
SSTL12 F10
SSTL12 F12
SSTL12 G3
SSTL12 F1
SSTL12 G11
SSTL12 F13
SSTL12 H13
SSTL12 D1
SSTL12 H11
SSTL12 D13
SSTL12 H3
SSTL12 G2
SSTL12 H4
SSTL12 H10
SSTL12 G12
SSTL12 H1
SSTL12 F2
SSTL12 G9
SSTL12 G5
SSTL12 H8
SSTL12 H6
SSTL12 F6
SSTL12 F8
SSTL12 H7
SSTL12 G7
www.xilinx.com
Chapter 3: Board Component Descriptions
Component Memory
Pin Name
QK2_B
QK3
QK3_B
QVLD0
QVLD1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
NF_A20
BA0
BA1
BA2
BA3
WE_B
REF_B
CK
CK_B
Send Feedback
Ref. Des.
U142
U142
U142
U142
U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
U141-U142
34