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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
#DDR4 C2
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS8_T"];
A8
[get_ports "DDR4_C1_DQS9_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS9_C"];
A9
[get_ports "DDR4_C1_DQS9_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C1_DQS9_T"];
F14
[get_ports "DDR4_C1_CK_T"];
DIFF_SSTL12_DCI
[get_ports "DDR4_C1_CK_T"];
E14
[get_ports "DDR4_C1_CK_C"];
DIFF_SSTL12_DCI
[get_ports "DDR4_C1_CK_C"];
A10
[get_ports "DDR4_C1_CKE"];
SSTL12_DCI
[get_ports "DDR4_C1_CKE"];
E13
[get_ports "DDR4_C1_ACT_B"];
SSTL12_DCI
[get_ports "DDR4_C1_ACT_B"];
R17
[get_ports "DDR4_C1_ALERT_B"];
SSTL12_DCI
[get_ports "DDR4_C1_ALERT_B"];
C8
[get_ports "DDR4_C1_ODT"];
SSTL12_DCI
[get_ports "DDR4_C1_ODT"];
G10
[get_ports "DDR4_C1_PAR"];
SSTL12_DCI
[get_ports "DDR4_C1_PAR"];
A20
[get_ports "DDR4_C1_TEN"];
SSTL12_DCI
[get_ports "DDR4_C1_TEN"];
F13
[get_ports "DDR4_C1_CS_B"];
SSTL12_DCI
[get_ports "DDR4_C1_CS_B"];
N20
[get_ports "DDR4_C1_RESET_B"];
LVCMOS12
[get_ports "DDR4_C1_RESET_B"];
BD30
[get_ports "DDR4_C2_DQ0"];
POD12_DCI
[get_ports "DDR4_C2_DQ0"];
BE30
[get_ports "DDR4_C2_DQ1"];
POD12_DCI
[get_ports "DDR4_C2_DQ1"];
BD32
[get_ports "DDR4_C2_DQ2"];
POD12_DCI
[get_ports "DDR4_C2_DQ2"];
BE33
[get_ports "DDR4_C2_DQ3"];
POD12_DCI
[get_ports "DDR4_C2_DQ3"];
BC33
[get_ports "DDR4_C2_DQ4"];
POD12_DCI
[get_ports "DDR4_C2_DQ4"];
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