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X-Ref Target - Figure 3-18
UTIL_3V3 to SYS_1V8
MAXIM_CABLE_B
PMBUS_ALERT
UTIL_3V3 to VCC1V2_FPGA
MAXIM_CABLE_B
PMBUS_ALERT
VCC1V8_FPGA
The TCA9548 U28 and U80 RESET_B pin 3 is connected to FPGA U1 Bank 64 pin AL25.
IMPORTANT:
FPGA pin AL25 LVCMOS18 net IIC_MUX_RESET_B must be driven High to enable I²C bus transactions
with the devices connected to U28 and U80.
User applications that communicate with devices on one of the downstream I
first set up a path to the desired target bus through the U28 or U80 bus switch at I
address 0x74 (0b1110100) or 0x75 (0b111101), respectively.
for each bus.
2
Table 3-27: I
C Bus Addresses
2
I
C Devices
TCA9548 8-Channel bus switch
SI570_1 clock
Not used
QSFP1 module
QSFP2 module
SI5328 clock
SI570_0 clock
FPGA SYSMON
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
U109
Level
shifters
SYS_1V8
always
BANK 501
enabled
SYS Controller
Q23
U111
FPGA U1
Q27
Level
BANK 42
shifter
VCC1V2_FPGA
always
enabled
VCC1V8_FPGA
BANK 64
Q21
UTIL_3V3 to
BANK 65
VCC1V8_FPGA
SYSMON IIC
Figure 3-18: VCU118 IIC Bus
2
I
C
Switch
Binary Format
Position
N/A
0b1110100
0
0b1011101
1
N/A
2
0b1010000
3
0b1010000
4
0b1101000
5
0b1011101
6
0b0110010
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Chapter 3: Board Component Descriptions
12V_SW
Maxim power
regulators
0x10 – 0x18
PMBUS SDA, SCL
IIC_MAIN
PMBUS
FMCP_HSPC
FMC_HPC1
EEPROM
IIC MUX1
INA_PMBUS
TCA9548
SI570_2
NC
U80
NC
0x75
SI570 x1
NC
QSFPI
QSFP2
IIC MUX1
SI5328
TCA9548
SI570_0
SYSMON
U28
FIREFLY
0x74
2
I
C Address
Hex Format
0x74
0x5D
N/A
0x50
0x50
0x68
0x5D
0x32
Maxim
Cable
0x11-0x1B, 0x70-0x73
0xx##
0xx##
0x50
0x40-0x45, 0x48
0x5D
0x5D
0x50
0x50
0x68
0x5D
0x32
0x50
X18025-102616
2
C buses must
2
C
Table 3-27
lists the address
Device
U28 TCA9548
U32 SI570
N/A
U145 28 Gb/s QSFP+
U123 28 Gb/s QSFP+
U57 SI5328B
U18 SI570
U1 BANK 65
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