Xilinx VCU118 User Manual page 29

Table 3-3: DDR4 Memory 80-bit I/F C2 to FPGA U1 Banks 40, 41, and 42 (Cont'd)
FPGA (U1)
Schematic Net Name
Pin
AV38 DDR4_C2_DQ62
AV39 DDR4_C2_DQ63
BA35 DDR4_C2_DQS6_T
BA36 DDR4_C2_DQS6_C
AW37 DDR4_C2_DQS7_T
AW38 DDR4_C2_DQS7_C
AY37 DDR4_C2_DM6
AV35 DDR4_C2_DM7
BF26 DDR4_C2_DQ64
BF27 DDR4_C2_DQ65
BD28 DDR4_C2_DQ66
BE28 DDR4_C2_DQ67
BD27 DDR4_C2_DQ68
BE27 DDR4_C2_DQ69
BD25 DDR4_C2_DQ70
BD26 DDR4_C2_DQ71
BC25 DDR4_C2_DQ72
BC26 DDR4_C2_DQ73
BB28 DDR4_C2_DQ74
BC28 DDR4_C2_DQ75
AY27 DDR4_C2_DQ76
AY28 DDR4_C2_DQ77
BA27 DDR4_C2_DQ78
BB27 DDR4_C2_DQ79
BE25 DDR4_C2_DQS8_T
BF25 DDR4_C2_DQS8_C
BA26 DDR4_C2_DQS9_T
BB26 DDR4_C2_DQS9_C
BE29 DDR4_C2_DM8
BA29 DDR4_C2_DM9
AM27 DDR4_C2_A0
AL27 DDR4_C2_A1
AP26 DDR4_C2_A2
AP25 DDR4_C2_A3
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Standard
POD12_DCI
POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
POD12_DCI
POD12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
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Chapter 3: Board Component Descriptions
Component Memory
Pin # Pin Name
D3 DQU6
D7 DQU7
G3 DQSL_C
F3 DQSL_T
B7 DQSU_C
A7 DQSU_T
E7 DML_B/DBIL_B
E2 DMU_B/DBIU_B
G2 DQL0
F7 DQL1
H3 DQL2
H7 DQL3
H2 DQL4
H8 DQL5
J3 DQL6
J7 DQL7
A3 DQU0
B8 DQU1
C3 DQU2
C7 DQU3
C2 DQU4
C8 DQU5
D3 DQU6
D7 DQU7
G3 DQSL_C
F3 DQSL_T
B7 DQSU_C
A7 DQSU_T
E7 DML_B/DBIL_B
E2 DMU_B/DBIU_B
P3 A0
P7 A1
R3 A2
N7 A3
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Ref. Des.
U138
U138
U138
U138
U138
U138
U138
U138
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U139
U135-U139
U135-U139
U135-U139
U135-U139
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