Xilinx VCU118 User Manual page 25

Table 3-2: DDR4 Memory 80-bit I/F C1 to FPGA U1 Banks 71, 72, and 73 (Cont'd)
FPGA (U1)
Schematic Net Name
Pin
C23 DDR4_C1_DQ67
B23 DDR4_C1_DQ68
B22 DDR4_C1_DQ69
B21 DDR4_C1_DQ70
A21 DDR4_C1_DQ71
D7 DDR4_C1_DQ72
C7 DDR4_C1_DQ73
B8 DDR4_C1_DQ74
B7 DDR4_C1_DQ75
C10 DDR4_C1_DQ76
B10 DDR4_C1_DQ77
B11 DDR4_C1_DQ78
A11 DDR4_C1_DQ79
D22 DDR4_C1_DQS8_T
C22 DDR4_C1_DQS8_C
A9 DDR4_C1_DQS9_T
A8 DDR4_C1_DQS9_C
E24 DDR4_C1_DM8
C9 DDR4_C1_DM9
D14 DDR4_C1_A0
B15 DDR4_C1_A1
B16 DDR4_C1_A2
C14 DDR4_C1_A3
C15 DDR4_C1_A4
A13 DDR4_C1_A5
A14 DDR4_C1_A6
A15 DDR4_C1_A7
A16 DDR4_C1_A8
B12 DDR4_C1_A9
C12 DDR4_C1_A10
B13 DDR4_C1_A11
C13 DDR4_C1_A12
D15 DDR4_C1_A13
G15 DDR4_C1_BA0
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Standard
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
POD12_DCI
POD12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
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Chapter 3: Board Component Descriptions
Component Memory
Pin # Pin Name
H7 DQL3
H2 DQL4
H8 DQL5
J3 DQL6
J7 DQL7
A3 DQU0
B8 DQU1
C3 DQU2
C7 DQU3
C2 DQU4
C8 DQU5
D3 DQU6
D7 DQU7
G3 DQSL_T
F3 DQSL_C
B7 DQSU_T
A7 DQSU_C
E7 DML_B/DBIL_B
E2 DMU_B/DBIU_B
P3 A0
P7 A1
R3 A2
N7 A3
N3 A4
P8 A5
P2 A6
R8 A7
R2 A8
R7 A9
M3 A10/AP
T2 A11
M7 A12/BC_B
T8 A13
N2 BA0
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Ref. Des.
U64
U64
U64
U64
U64
U64
U64
U64
U64
U64
U64
U64
U64
U64
U64
U64
U64
U64
U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
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