Xilinx VCU118 User Manual page 136

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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
SSTL12
[get_ports "RLD3_C3_72B_DQ53"];
H27
[get_ports "RLD3_C3_72B_DQ54"];
SSTL12
[get_ports "RLD3_C3_72B_DQ54"];
G27
[get_ports "RLD3_C3_72B_DQ55"];
SSTL12
[get_ports "RLD3_C3_72B_DQ55"];
F28
[get_ports "RLD3_C3_72B_DQ56"];
SSTL12
[get_ports "RLD3_C3_72B_DQ56"];
E28
[get_ports "RLD3_C3_72B_DQ57"];
SSTL12
[get_ports "RLD3_C3_72B_DQ57"];
H28
[get_ports "RLD3_C3_72B_DQ58"];
SSTL12
[get_ports "RLD3_C3_72B_DQ58"];
G28
[get_ports "RLD3_C3_72B_DQ59"];
SSTL12
[get_ports "RLD3_C3_72B_DQ59"];
E26
[get_ports "RLD3_C3_72B_DQ60"];
SSTL12
[get_ports "RLD3_C3_72B_DQ60"];
E27
[get_ports "RLD3_C3_72B_DQ61"];
SSTL12
[get_ports "RLD3_C3_72B_DQ61"];
G25
[get_ports "RLD3_C3_72B_DQ62"];
SSTL12
[get_ports "RLD3_C3_72B_DQ62"];
B28
[get_ports "RLD3_C3_72B_DQ63"];
SSTL12
[get_ports "RLD3_C3_72B_DQ63"];
A28
[get_ports "RLD3_C3_72B_DQ64"];
SSTL12
[get_ports "RLD3_C3_72B_DQ64"];
C27
[get_ports "RLD3_C3_72B_DQ65"];
SSTL12
[get_ports "RLD3_C3_72B_DQ65"];
B27
[get_ports "RLD3_C3_72B_DQ66"];
SSTL12
[get_ports "RLD3_C3_72B_DQ66"];
B26
[get_ports "RLD3_C3_72B_DQ67"];
SSTL12
[get_ports "RLD3_C3_72B_DQ67"];
A26
[get_ports "RLD3_C3_72B_DQ68"];
SSTL12
[get_ports "RLD3_C3_72B_DQ68"];
D25
[get_ports "RLD3_C3_72B_DQ69"];
SSTL12
[get_ports "RLD3_C3_72B_DQ69"];
D26
[get_ports "RLD3_C3_72B_DQ70"];
SSTL12
[get_ports "RLD3_C3_72B_DQ70"];
C25
[get_ports "RLD3_C3_72B_DQ71"];
SSTL12
[get_ports "RLD3_C3_72B_DQ71"];
A29
[get_ports "RLD3_C3_72B_A0"];
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