Xilinx VCU118 User Manual page 28

Table 3-3: DDR4 Memory 80-bit I/F C2 to FPGA U1 Banks 40, 41, and 42 (Cont'd)
FPGA (U1)
Schematic Net Name
Pin
BC35 DDR4_C2_DQ34
BC36 DDR4_C2_DQ35
BD36 DDR4_C2_DQ36
BE37 DDR4_C2_DQ37
BF36 DDR4_C2_DQ38
BF37 DDR4_C2_DQ39
BD37 DDR4_C2_DQ40
BE38 DDR4_C2_DQ41
BC39 DDR4_C2_DQ42
BD40 DDR4_C2_DQ43
BB38 DDR4_C2_DQ44
BB39 DDR4_C2_DQ45
BC38 DDR4_C2_DQ46
BD38 DDR4_C2_DQ47
BE35 DDR4_C2_DQS4_T
BF35 DDR4_C2_DQS4_C
BE39 DDR4_C2_DQS5_T
BF39 DDR4_C2_DQS5_C
BC34 DDR4_C2_DM4
BE40 DDR4_C2_DM5
BB36 DDR4_C2_DQ48
BB37 DDR4_C2_DQ49
BA39 DDR4_C2_DQ50
BA40 DDR4_C2_DQ51
AW40 DDR4_C2_DQ52
AY40 DDR4_C2_DQ53
AY38 DDR4_C2_DQ54
AY39 DDR4_C2_DQ55
AW35 DDR4_C2_DQ56
AW36 DDR4_C2_DQ57
AU40 DDR4_C2_DQ58
AV40 DDR4_C2_DQ59
AU38 DDR4_C2_DQ60
AU39 DDR4_C2_DQ61
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Standard
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
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Chapter 3: Board Component Descriptions
Component Memory
Pin # Pin Name
H3 DQL2
H7 DQL3
H2 DQL4
H8 DQL5
J3 DQL6
J7 DQL7
A3 DQU0
B8 DQU1
C3 DQU2
C7 DQU3
C2 DQU4
C8 DQU5
D3 DQU6
D7 DQU7
G3 DQSL_T
F3 DQSL_C
B7 DQSU_T
A7 DQSU_C
E7 DML_B/DBIL_B
E2 DMU_B/DBIU_B
G2 DQL0
F7 DQL1
H3 DQL2
H7 DQL3
H2 DQL4
H8 DQL5
J3 DQL6
J7 DQL7
A3 DQU0
B8 DQU1
C3 DQU2
C7 DQU3
C2 DQU4
C8 DQU5
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Ref. Des.
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U137
U138
U138
U138
U138
U138
U138
U138
U138
U138
U138
U138
U138
U138
U138
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