Xilinx VCU118 User Manual page 97

Table 3-31: J2 VITA 57.1 FMC HPC1 Connections (Cont'd)
J2
FMC
Schematic Net Name
HPC1
Pin
Notes:
1. U30 MAX15301 VADJ_1V8_FPGA voltage regulator PGOOD level-shifted by U44.
2. FPGA U1 JTAG TCK, TMS pins AE13, AF15 are buffered by U19 SN74AVC8T245.
3. J2 HPC1 TDO-TDI connections to U132 HPC1 FMC JTAG bypass switch (N.C. normally closes/bypassing J2 until an FMC card
is plugged into J2).
4. FMC_HPC1_PRSNT_M2C_B is the HPC1 FMC JTAG bypass switch U132.4 OE control signal and is also connected to the FPGA
U1 pin BB7 via level shifter U44.
5. Connected to the FPGA U1 pins AL24/AM24 IIC_MAIN_SDA/SCL via IIC MUX U80.
6. HPC1 FMC signal FMC_HPC1_PG_M2C is connected to the FPGA U1 pin BA7 via level shifter U44.
The VCU118 evaluation board supports the VITA 57.4 FPGA mezzanine card plus (FMC+ or
FMCP) specification by providing a subset implementations of the high pin count
connectors at J22 (HSPC). FMC+ connectors use a 14 x 40 form factor, populated with 560
pins. The connector is keyed so that a mezzanine card, when installed on the VCU118
evaluation board, faces away from the board.
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
J2
FPGA
I/O FMC
(U1)
Standard HPC1
Pin
Pin
J2 Sections J/K are no connects (not connected to FPGA U1)
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Chapter 3: Board Component Descriptions
Schematic Net Name
Send Feedback
I/O FPGA
Standard (U1) Pin
97