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set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
AV38
[get_ports "DDR4_C2_DQ62"];
POD12_DCI
[get_ports "DDR4_C2_DQ62"];
AV39
[get_ports "DDR4_C2_DQ63"];
POD12_DCI
[get_ports "DDR4_C2_DQ63"];
BF26
[get_ports "DDR4_C2_DQ64"];
POD12_DCI
[get_ports "DDR4_C2_DQ64"];
BF27
[get_ports "DDR4_C2_DQ65"];
POD12_DCI
[get_ports "DDR4_C2_DQ65"];
BD28
[get_ports "DDR4_C2_DQ66"];
POD12_DCI
[get_ports "DDR4_C2_DQ66"];
BE28
[get_ports "DDR4_C2_DQ67"];
POD12_DCI
[get_ports "DDR4_C2_DQ67"];
BD27
[get_ports "DDR4_C2_DQ68"];
POD12_DCI
[get_ports "DDR4_C2_DQ68"];
BE27
[get_ports "DDR4_C2_DQ69"];
POD12_DCI
[get_ports "DDR4_C2_DQ69"];
BD25
[get_ports "DDR4_C2_DQ70"];
POD12_DCI
[get_ports "DDR4_C2_DQ70"];
BD26
[get_ports "DDR4_C2_DQ71"];
POD12_DCI
[get_ports "DDR4_C2_DQ71"];
BC25
[get_ports "DDR4_C2_DQ72"];
POD12_DCI
[get_ports "DDR4_C2_DQ72"];
BC26
[get_ports "DDR4_C2_DQ73"];
POD12_DCI
[get_ports "DDR4_C2_DQ73"];
BB28
[get_ports "DDR4_C2_DQ74"];
POD12_DCI
[get_ports "DDR4_C2_DQ74"];
BC28
[get_ports "DDR4_C2_DQ75"];
POD12_DCI
[get_ports "DDR4_C2_DQ75"];
AY27
[get_ports "DDR4_C2_DQ76"];
POD12_DCI
[get_ports "DDR4_C2_DQ76"];
AY28
[get_ports "DDR4_C2_DQ77"];
POD12_DCI
[get_ports "DDR4_C2_DQ77"];
BA27
[get_ports "DDR4_C2_DQ78"];
POD12_DCI
[get_ports "DDR4_C2_DQ78"];
BB27
[get_ports "DDR4_C2_DQ79"];
POD12_DCI
[get_ports "DDR4_C2_DQ79"];
AM27
[get_ports "DDR4_C2_A0 "];
SSTL12_DCI
[get_ports "DDR4_C2_A0 "];
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