Xilinx VCU118 User Manual page 35

Table 3-4: RLD3 Memory 72-bit I/F to FPGA U1 Banks 46, 47, and 48 (Cont'd)
FPGA
Schematic Net Name
(U1) Pin
L29 RLD3_C3_72B_RESET_B
N29 RLD3_C3_72B_CS_B
K31 RLD3_C3_72B_DK0_P
J31 RLD3_C3_72B_DK0_N
K32 RLD3_C3_72B_DK1_P
J32 RLD3_C3_72B_DK1_N
J29 RLD3_C3_72B_DK2_P
J30 RLD3_C3_72B_DK2_N
H33 RLD3_C3_72B_DK3_P
G33 RLD3_C3_72B_DK3_N
The VCU118 RLD3 72-bit memory component interface adheres to the constraints
guidelines documented in the RLD3 Design Guidelines section of UltraScale
Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)
VCU118 RLD3 memory component interface is a 40Ω impedance implementation. For more
information on the internal VREF, see the "Supply Voltages for the SelectIO Pins", "V
and "Internal V
For more details about the Micron RLD3 component memory, see the Micron
MT44K32M36RB-083E Data Sheet
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Standard
SSTL12
SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
" sections in UltraScale Architecture SelectIO Resources (UG571)
REF
[Ref
www.xilinx.com
Chapter 3: Board Component Descriptions
Component Memory
Pin #
A13
E12
D7
C7
K7
L7
D7
C7
K7
L7
18].
Pin Name Ref. Des.
RESET_B U141-U142
CS_B U141-U142
DK0 U141
DK0_B U141
DK1 U141
DK1_B U141
DK0 U142
DK0_B U142
DK1 U142
DK1_B U142
[Ref 4]. The
[Ref
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",
REF
3].
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