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set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
BE35
[get_ports "DDR4_C2_DQS4_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS4_T"];
BF39
[get_ports "DDR4_C2_DQS5_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS5_C"];
BE39
[get_ports "DDR4_C2_DQS5_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS5_T"];
BA36
[get_ports "DDR4_C2_DQS6_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS6_C"];
BA35
[get_ports "DDR4_C2_DQS6_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS6_T"];
AW38
[get_ports "DDR4_C2_DQS7_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS7_C"];
AW37
[get_ports "DDR4_C2_DQS7_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS7_T"];
BF25
[get_ports "DDR4_C2_DQS8_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS8_C"];
BE25
[get_ports "DDR4_C2_DQS8_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS8_T"];
BB26
[get_ports "DDR4_C2_DQS9_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS9_C"];
BA26
[get_ports "DDR4_C2_DQS9_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS9_T"];
AT26
[get_ports "DDR4_C2_CK_T"];
DIFF_SSTL12_DCI
[get_ports "DDR4_C2_CK_T"];
AT27
[get_ports "DDR4_C2_CK_C"];
DIFF_SSTL12_DCI
[get_ports "DDR4_C2_CK_C"];
AW28
[get_ports "DDR4_C2_CKE"];
SSTL12_DCI
[get_ports "DDR4_C2_CKE"];
AN25
[get_ports "DDR4_C2_ACT_B"];
SSTL12_DCI
[get_ports "DDR4_C2_ACT_B"];
AR29
[get_ports "DDR4_C2_ALERT_B"];
SSTL12_DCI
[get_ports "DDR4_C2_ALERT_B"];
BB29
[get_ports "DDR4_C2_ODT"];
SSTL12_DCI
[get_ports "DDR4_C2_ODT"];
BF29
[get_ports "DDR4_C2_PAR"];
SSTL12_DCI
[get_ports "DDR4_C2_PAR"];
AY35
[get_ports "DDR4_C2_TEN"];
SSTL12_DCI
[get_ports "DDR4_C2_TEN"];
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