Xilinx VCU118 User Manual page 154

set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
# IIC MUX RESET
set_property PACKAGE_PIN
set_property IOSTANDARD
# ETHERNET PHY
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
# SYSTEM CONTROLLER
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
LVCMOS18 [get_ports "IIC_MAIN_SCL"];
AL24 [get_ports "IIC_MAIN_SDA"];
LVCMOS18 [get_ports "IIC_MAIN_SDA"];
AL25 [get_ports "IIC_MUX_RESET_B"];
LVCMOS18 [get_ports "IIC_MUX_RESET_B"];
AU23 [get_ports "PHY1_CLKOUT"];
LVCMOS18 [get_ports "PHY1_CLKOUT"];
AR22 [get_ports "PHY1_GPIO_0"];
LVCMOS18 [get_ports "PHY1_GPIO_0"];
AV23 [get_ports "PHY1_MDC "];
LVCMOS18 [get_ports "PHY1_MDC "];
AR23 [get_ports "PHY1_MDIO"];
LVCMOS18 [get_ports "PHY1_MDIO"];
AR24 [get_ports "PHY1_PDWN_B_I_INT_B_O"];
LVCMOS18 [get_ports "PHY1_PDWN_B_I_INT_B_O"];
BA21 [get_ports "PHY1_RESET_B"];
LVCMOS18 [get_ports "PHY1_RESET_B"];
AU22 [get_ports "PHY1_SGMII_CLK_N"];
DIFF_HSTL_I_18 [get_ports "PHY1_SGMII_CLK_N"];
AT22 [get_ports "PHY1_SGMII_CLK_P"];
DIFF_HSTL_I_18 [get_ports "PHY1_SGMII_CLK_P"];
AV21 [get_ports "PHY1_SGMII_IN_N"];
DIFF_HSTL_I_18 [get_ports "PHY1_SGMII_IN_N"];
AU21 [get_ports "PHY1_SGMII_IN_P"];
DIFF_HSTL_I_18 [get_ports "PHY1_SGMII_IN_P"];
AV24 [get_ports "PHY1_SGMII_OUT_N"];
DIFF_HSTL_I_18 [get_ports "PHY1_SGMII_OUT_N"];
AU24 [get_ports "PHY1_SGMII_OUT_P"];
DIFF_HSTL_I_18 [get_ports "PHY1_SGMII_OUT_P"];
BD21 [get_ports "SYSCTLR_GPIO_5"];
LVCMOS18 [get_ports "SYSCTLR_GPIO_5"];
BA25 [get_ports "SYSCTLR_GPIO_6"];
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