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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
POD12_DCI
[get_ports "DDR4_C1_DQ13"];
N17
[get_ports "DDR4_C1_DQ14"];
POD12_DCI
[get_ports "DDR4_C1_DQ14"];
M16
[get_ports "DDR4_C1_DQ15"];
POD12_DCI
[get_ports "DDR4_C1_DQ15"];
L16
[get_ports "DDR4_C1_DQ16"];
POD12_DCI
[get_ports "DDR4_C1_DQ16"];
K16
[get_ports "DDR4_C1_DQ17"];
POD12_DCI
[get_ports "DDR4_C1_DQ17"];
L18
[get_ports "DDR4_C1_DQ18"];
POD12_DCI
[get_ports "DDR4_C1_DQ18"];
K18
[get_ports "DDR4_C1_DQ19"];
POD12_DCI
[get_ports "DDR4_C1_DQ19"];
J17
[get_ports "DDR4_C1_DQ20"];
POD12_DCI
[get_ports "DDR4_C1_DQ20"];
H17
[get_ports "DDR4_C1_DQ21"];
POD12_DCI
[get_ports "DDR4_C1_DQ21"];
H19
[get_ports "DDR4_C1_DQ22"];
POD12_DCI
[get_ports "DDR4_C1_DQ22"];
H18
[get_ports "DDR4_C1_DQ23"];
POD12_DCI
[get_ports "DDR4_C1_DQ23"];
F19
[get_ports "DDR4_C1_DQ24"];
POD12_DCI
[get_ports "DDR4_C1_DQ24"];
F18
[get_ports "DDR4_C1_DQ25"];
POD12_DCI
[get_ports "DDR4_C1_DQ25"];
E19
[get_ports "DDR4_C1_DQ26"];
POD12_DCI
[get_ports "DDR4_C1_DQ26"];
E18
[get_ports "DDR4_C1_DQ27"];
POD12_DCI
[get_ports "DDR4_C1_DQ27"];
G20
[get_ports "DDR4_C1_DQ28"];
POD12_DCI
[get_ports "DDR4_C1_DQ28"];
F20
[get_ports "DDR4_C1_DQ29"];
POD12_DCI
[get_ports "DDR4_C1_DQ29"];
E17
[get_ports "DDR4_C1_DQ30"];
POD12_DCI
[get_ports "DDR4_C1_DQ30"];
D16
[get_ports "DDR4_C1_DQ31"];
POD12_DCI
[get_ports "DDR4_C1_DQ31"];
D17
[get_ports "DDR4_C1_DQ32"];
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