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set_property IOSTANDARD
# PMOD1
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
# PCIE
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
# FAN
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
# MAXIM CABLE
set_property PACKAGE_PIN
set_property IOSTANDARD
# PMBUS
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
LVCMOS12
[get_ports "PMOD0_7_LS "];
N28
[get_ports "PMOD1_0_LS "];
LVCMOS12
[get_ports "PMOD1_0_LS "];
M30
[get_ports "PMOD1_1_LS "];
LVCMOS12
[get_ports "PMOD1_1_LS "];
N30
[get_ports "PMOD1_2_LS "];
LVCMOS12
[get_ports "PMOD1_2_LS "];
P30
[get_ports "PMOD1_3_LS "];
LVCMOS12
[get_ports "PMOD1_3_LS "];
P29
[get_ports "PMOD1_4_LS "];
LVCMOS12
[get_ports "PMOD1_4_LS "];
L31
[get_ports "PMOD1_5_LS "];
LVCMOS12
[get_ports "PMOD1_5_LS "];
M31
[get_ports "PMOD1_6_LS "];
LVCMOS12
[get_ports "PMOD1_6_LS "];
R29
[get_ports "PMOD1_7_LS "];
LVCMOS12
[get_ports "PMOD1_7_LS "];
AM17
[get_ports "PCIE_PERST_LS"];
LVCMOS18
[get_ports "PCIE_PERST_LS"];
BC24
[get_ports "PCIE_WAKE_B_LS"];
LVCMOS18
[get_ports "PCIE_WAKE_B_LS"];
BA10
[get_ports "SM_FAN_PWM "];
LVCMOS18
[get_ports "SM_FAN_PWM "];
BF7
[get_ports "SM_FAN_TACH"];
LVCMOS18
[get_ports "SM_FAN_TACH"];
BF40
[get_ports "MAXIM_CABLE_LS_B"];
LVCMOS12
[get_ports "MAXIM_CABLE_LS_B"];
BB23
[get_ports "PMBUS_ALERT_FPGA"];
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