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Table 3-6: VCU118 Board Clock Sources (Cont'd)
Clock Name
QSFP2 Jitter attenuated clock
User SMA clock
QSFP clock 10 MHz-810 MHz
Fixed 250 MHz
Table 3-7
lists the VCU118 clock sources to FPGA U1 connections.
Table 3-7: VCU118 Clock Sources to XCVU9P FPGA U1 Connections
Clock Source
Device/U#.Pin#
SI53340/U157.9
SI53340/U157.10
SI5335A/U122.18
SI5335A/U122.17
SI5335A/U122.14
SI5335A/U122.10
SI53340/U104.9
SI53340/U104.10
SI53340/U157.13
SI53340/U157.14
SI53340/U104.11
SI53340/U104.12
SI53340/U104.13
SI53340/U104.14
SI53340/U104.15
SI53340/U104.16
SI5328B/U57.28
SI5328B/U57.29
SI5328B/U57.28
SI5328B/U57.29
SMA/J34.1
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Clock Ref. Des.
Silicon Labs Si5328B LVDS precision clock
U57
multiplier/jitter attenuator. See
Clock
User clock input SMAs. See
J34(P), J35(N)
(USER_SMA_CLOCK_P and USER_SMA_CLOCK_N).
Silicon Labs Si570 3.3V LVDS I
U38
oscillator, 156.250 MHz default.
(QSFP_SI570_CLOCK_P/N)
Epson SG5032 3.3V LVDS I
U14/U21
MHz. U14 output drives U21 dual clock buffer.
(250MHZ_CLK1_P/N and 250MHZ_CLK2_P/N)
Schematic Net Name
SYSCLK1_300_P
SYSCLK1_300_N
CLK_125MHZ_P
CLK_125MHZ_N
(2)
FPGA_EMCCLK
(2)
SYSCTLR_CLK
USER_SI570_CLOCK_P
USER_SI570_CLOCK_N
USER_SI570_CLOCK1_P
USER_SI570_CLOCK1_N
MGT_SI570_CLOCK1_P
MGT_SI570_CLOCK1_N
MGT_SI570_CLOCK2_P
MGT_SI570_CLOCK2_N
MGT_SI570_CLOCK3_P
MGT_SI570_CLOCK3_N
SI5328_OUT1_P
SI5328_OUT1_N
SI5328_OUT2_P
SI5328_OUT2_N
USER_SMA_CLOCK_P
www.xilinx.com
Chapter 3: Board Component Descriptions
Description
(SI5328_OUT2_P/N)
User SMA Clock
2
C programmable
2
C oscillator, fixed 250
I/O Standard
LVDS
LVDS
LVDS
LVDS
LVCMOS18
LVCMOS18
LVDS
LVDS
LVDS
LVDS
(2)
NA
(2)
NA
(2)
NA
(2)
NA
(2)
NA
(2)
NA
(1)
NA
(1)
NA
(1)
NA
(1)
NA
LVDS
Send Feedback
Jitter Attenuated
FPGA (U1) Pin
G31
F31
AY24
AY23
AL20
U111.C7
H32
G32
AW23
AW22
AJ9
AJ8
R9
R8
L9
L8
U9
U8
N9
N8
R32
42
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