Xilinx VCU118 User Manual page 133

set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
#RLD3 C3
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
AY29 [get_ports "DDR4_C2_CS_B"];
LVCMOS12 [get_ports "DDR4_C2_CS_B"];
BD35 [get_ports "DDR4_C2_RESET_B"];
SSTL12_DCI [get_ports "DDR4_C2_RESET_B"];
H39 [get_ports "RLD3_C3_72B_DQ0"];
SSTL12 [get_ports "RLD3_C3_72B_DQ0"];
H40 [get_ports "RLD3_C3_72B_DQ1"];
SSTL12 [get_ports "RLD3_C3_72B_DQ1"];
G40 [get_ports "RLD3_C3_72B_DQ2"];
SSTL12 [get_ports "RLD3_C3_72B_DQ2"];
F40 [get_ports "RLD3_C3_72B_DQ3"];
SSTL12 [get_ports "RLD3_C3_72B_DQ3"];
H38 [get_ports "RLD3_C3_72B_DQ4"];
SSTL12 [get_ports "RLD3_C3_72B_DQ4"];
G38 [get_ports "RLD3_C3_72B_DQ5"];
SSTL12 [get_ports "RLD3_C3_72B_DQ5"];
K37 [get_ports "RLD3_C3_72B_DQ6"];
SSTL12 [get_ports "RLD3_C3_72B_DQ6"];
J37 [get_ports "RLD3_C3_72B_DQ7"];
SSTL12 [get_ports "RLD3_C3_72B_DQ7"];
F38 [get_ports "RLD3_C3_72B_DQ8"];
SSTL12 [get_ports "RLD3_C3_72B_DQ8"];
J35 [get_ports "RLD3_C3_72B_DQ9"];
SSTL12 [get_ports "RLD3_C3_72B_DQ9"];
H35 [get_ports "RLD3_C3_72B_DQ10"];
SSTL12 [get_ports "RLD3_C3_72B_DQ10"];
J36 [get_ports "RLD3_C3_72B_DQ11"];
SSTL12 [get_ports "RLD3_C3_72B_DQ11"];
H37 [get_ports "RLD3_C3_72B_DQ12"];
SSTL12 [get_ports "RLD3_C3_72B_DQ12"];
H34 [get_ports "RLD3_C3_72B_DQ13"];
SSTL12 [get_ports "RLD3_C3_72B_DQ13"];
G35 [get_ports "RLD3_C3_72B_DQ14"];
SSTL12 [get_ports "RLD3_C3_72B_DQ14"];
F35 [get_ports "RLD3_C3_72B_DQ15"];
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