Xilinx VCU118 User Manual page 74

Table 3-23: VCU118 Board FPGA U1 to QSFP+ Module QSFP2 U123 Connections
FPGA
FPGA (U1) Pin Name
(U1) Pin
L5 MGTYTXP0_232
L4 MGTYTXN0_232
T2 MGTYRXP0_232
T1 MGTYRXN0_232
K7 MGTYTXP1_232
K6 MGTYTXN1_232
R4 MGTYRXP1_232
R3 MGTYRXN1_232
J5 MGTYTXP2_232
J4 MGTYTXN2_232
P2 MGTYRXP2_232
P1 MGTYRXN2_232
H7 MGTYTXP3_232
H6 MGTYTXN3_232
M2 MGTYRXP3_232
M1 MGTYRXN3_232
U28.11
U28.10
AN23 IO_L20N_T3L_N3_AD1N_64
AY22 IO_L10P_T1U_N6_QBC_AD4P_64
AN24 IO_L20P_T3L_N2_AD1P_64
AT21 IO_T2U_N12_64
AT24 IO_L18N_T2U_N11_AD2N_64
Notes:
1. The QSFP+ connector U123 I
Topology, and Switches.
2. The QSFP+ connector U123 QSFP2 control signals are level-shifted by U3.
For additional information about the quad small form factor pluggable (28 Gb/s QSFP+) module, see the SFF-8663
specification for the 28 Gb/s QSFP+ at the SFF-8663 specification website
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Schematic Net Name
SC3 QSFP2_IIC_SCL(1)
SD3 QSFP2_IIC_SDA(1)
QSFP2_MODSELL(2)
QSFP2_RESETL(2)
QSFP2_MODPRSL(2)
QSFP2_LPMODE(2)
2
C SCL/SDA IS connected to the I
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Chapter 3: Board Component Descriptions
FPGA (U1)
Direction
QSFP2_TX1_P Output
QSFP2_TX1_N Output
QSFP2_RX1_P Input
QSFP2_RX1_N Input
QSFP2_TX2_P Output
QSFP2_TX2_N Output
QSFP2_RX2_P Input
QSFP2_RX2_N Input
QSFP2_TX3_P Output
QSFP2_TX3_N Output
QSFP2_RX3_P Input
QSFP2_RX3_N Input
QSFP2_TX4_P Output
QSFP2_TX4_N Output
QSFP2_RX4_P Input
QSFP2_RX4_N Input
Output
BiDir
Output
Output
Output
QSFP2_INTL(2) Input
Output
2
C switch U28 to the IIC_MAIN_SCL/SDA bus. See
[Ref 24].
QSFP2 U123
Pin Num Pin Name
36 TX1P
37 TX1N
17 RX1P
18 RX1N
3 TX2P
2 TX2N
22 RX2P
21 RX2N
33 TX3P
34 TX3N
14 RX3P
15 RX3N
6 TX4P
5 TX4N
25 RX4P
24 RX4N
11 SCL
12 SDA
8 MODSELL
9 RESETL
27 MODPRSL
28 INTL
31 LPMODE
I2C Bus,
74
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