Xilinx VCU118 User Manual page 118

set_property IOSTANDARD
# SI5328
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
# DDR4 C1
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
LVDS [get_ports "USER_SI570_CLOCK1_N"];
H20 [get_ports "SI5328_INT_ALM_LS"];
LVCMOS12 [get_ports "SI5328_INT_ALM_LS"];
BC21 [get_ports "SI5328_RST_LS"];
LVCMOS12 [get_ports "SI5328_RST_LS"];
F11 [get_ports "DDR4_C1_DQ0"];
POD12_DCI [get_ports "DDR4_C1_DQ0"];
E11 [get_ports "DDR4_C1_DQ1"];
POD12_DCI [get_ports "DDR4_C1_DQ1"];
F10 [get_ports "DDR4_C1_DQ2"];
POD12_DCI [get_ports "DDR4_C1_DQ2"];
F9 [get_ports "DDR4_C1_DQ3"];
POD12_DCI [get_ports "DDR4_C1_DQ3"];
H12 [get_ports "DDR4_C1_DQ4"];
POD12_DCI [get_ports "DDR4_C1_DQ4"];
G12 [get_ports "DDR4_C1_DQ5"];
POD12_DCI [get_ports "DDR4_C1_DQ5"];
E9 [get_ports "DDR4_C1_DQ6"];
POD12_DCI [get_ports "DDR4_C1_DQ6"];
D9 [get_ports "DDR4_C1_DQ7"];
POD12_DCI [get_ports "DDR4_C1_DQ7"];
R19 [get_ports "DDR4_C1_DQ8"];
POD12_DCI [get_ports "DDR4_C1_DQ8"];
P19 [get_ports "DDR4_C1_DQ9"];
POD12_DCI [get_ports "DDR4_C1_DQ9"];
M18 [get_ports "DDR4_C1_DQ10"];
POD12_DCI [get_ports "DDR4_C1_DQ10"];
M17 [get_ports "DDR4_C1_DQ11"];
POD12_DCI [get_ports "DDR4_C1_DQ11"];
N19 [get_ports "DDR4_C1_DQ12"];
POD12_DCI [get_ports "DDR4_C1_DQ12"];
N18 [get_ports "DDR4_C1_DQ13"];
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