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Table 3-12: VCU118 FPGA U1 GTY Transceiver Bank 126 Connections
FPGA
MGT
FPGA (U1) Pin
(U1)
Bank
Name
Pin
T42
MGTYTXP0_126
T43
MGTYTXN0_126
W45
MGTYRXP0_126
W46
MGTYRXN0_126
P42
MGTYTXP1_126
P43
MGTYTXN1_126
U45
MGTYRXP1_126
U46
MGTYRXN1_126
M42
MGTYTXP2_126
M43
MGTYTXN2_126
GTY
R45
MGTYRXP2_126
Bank
R46
MGTYRXN2_126
126
K42
MGTYTXP3_126
K43
MGTYTXN3_126
N45
MGTYRXP3_126
N46
MGTYRXN3_126
V38
MGTREFCLK0P_126
V39
MGTREFCLK0N_126
T38
MGTREFCLK1P_126
T39
MGTREFCLK1N_126
L41
MGTRREF_LN
L40
MGTAVTTRCAL_LN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Schematic Net Name
FMCP_HSPC_DP4_C2M_P
FMCP_HSPC_DP4_C2M_N
FMCP_HSPC_DP4_M2C_P
FMCP_HSPC_DP4_M2C_N
FMCP_HSPC_DP5_C2M_P
FMCP_HSPC_DP5_C2M_N
FMCP_HSPC_DP5_M2C_P
FMCP_HSPC_DP5_M2C_N
FMCP_HSPC_DP6_C2M_P
FMCP_HSPC_DP6_C2M_N
FMCP_HSPC_DP6_M2C_P
FMCP_HSPC_DP6_M2C_N
FMCP_HSPC_DP7_C2M_P
FMCP_HSPC_DP7_C2M_N
FMCP_HSPC_DP7_M2C_P
FMCP_HSPC_DP7_M2C_N
FMCP_HSPC_GBT0_1_P
FMCP_HSPC_GBT0_1_N
FMCP_HSPC_GBT1_1_P
FMCP_HSPC_GBT1_1_N
MGTRREF_126
MGTAVTT_FPGA
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Chapter 3: Board Component Descriptions
Connected
Connected Pin
Pin
Name
A34
DP4_C2M_P
A35
DP4_C2M_N
A14
DP4_M2C_P
A15
DP4_M2C_N
A38
DP5_C2M_P
A39
DP5_C2M_N
A18
DP5_M2C_P
A19
DP5_M2C_N
B36
DP6_C2M_P
B37
DP6_C2M_N
B16
DP6_M2C_P
B17
DP6_M2C_N
B32
DP7_C2M_P
B33
DP7_C2M_N
B12
DP7_M2C_P
B13
DP7_M2C_N
3
Q1
4
NQ1
8
Q1_P
9
Q1_N
R176.1 100Ω 1% P/U to MGTAVTT_FPGA
NA
NA
Send Feedback
Connected Device
FMC+ HSPC J22
U40 ICS85411A
clock buffer
U39 ICS855S006I
clock buffer
NA
58
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