Xilinx VCU118 User Manual page 139

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set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK0_P"];
E34
[get_ports "RLD3_C3_72B_QK1_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK1_N"];
F34
[get_ports "RLD3_C3_72B_QK1_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK1_P"];
D39
[get_ports "RLD3_C3_72B_QK2_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK2_N"];
E39
[get_ports "RLD3_C3_72B_QK2_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK2_P"];
C37
[get_ports "RLD3_C3_72B_QK3_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK3_N"];
D37
[get_ports "RLD3_C3_72B_QK3_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK3_P"];
R26
[get_ports "RLD3_C3_72B_QK4_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK4_N"];
T26
[get_ports "RLD3_C3_72B_QK4_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK4_P"];
M28
[get_ports "RLD3_C3_72B_QK5_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK5_N"];
M27
[get_ports "RLD3_C3_72B_QK5_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK5_P"];
F26
[get_ports "RLD3_C3_72B_QK6_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK6_N"];
G26
[get_ports "RLD3_C3_72B_QK6_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK6_P"];
C28
[get_ports "RLD3_C3_72B_QK7_N"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK7_N"];
D27
[get_ports "RLD3_C3_72B_QK7_P"];
DIFF_SSTL12
[get_ports "RLD3_C3_72B_QK7_P"];
G37
[get_ports "RLD3_C3_72B_QVLD0"];
SSTL12
[get_ports "RLD3_C3_72B_QVLD0"];
A38
[get_ports "RLD3_C3_72B_QVLD1"];
SSTL12
[get_ports "RLD3_C3_72B_QVLD1"];
J27
[get_ports "RLD3_C3_72B_QVLD2"];
SSTL12
[get_ports "RLD3_C3_72B_QVLD2"];
F25
[get_ports "RLD3_C3_72B_QVLD3"];
SSTL12
[get_ports "RLD3_C3_72B_QVLD3"];
H29
[get_ports "RLD3_C3_72B_CK_P"];
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