Xilinx VCU118 User Manual page 33

Table 3-4: RLD3 Memory 72-bit I/F to FPGA U1 Banks 46, 47, and 48 (Cont'd)
FPGA
Schematic Net Name
(U1) Pin
M25 RLD3_C3_72B_DQ45
L26 RLD3_C3_72B_DQ46
L28 RLD3_C3_72B_DQ47
K28 RLD3_C3_72B_DQ48
L24 RLD3_C3_72B_DQ49
L25 RLD3_C3_72B_DQ50
K26 RLD3_C3_72B_DQ51
J26 RLD3_C3_72B_DQ52
K27 RLD3_C3_72B_DQ53
H27 RLD3_C3_72B_DQ54
G27 RLD3_C3_72B_DQ55
F28 RLD3_C3_72B_DQ56
E28 RLD3_C3_72B_DQ57
H28 RLD3_C3_72B_DQ58
G28 RLD3_C3_72B_DQ59
E26 RLD3_C3_72B_DQ60
E27 RLD3_C3_72B_DQ61
G25 RLD3_C3_72B_DQ62
B28 RLD3_C3_72B_DQ63
A28 RLD3_C3_72B_DQ64
C27 RLD3_C3_72B_DQ65
B27 RLD3_C3_72B_DQ66
B26 RLD3_C3_72B_DQ67
A26 RLD3_C3_72B_DQ68
D25 RLD3_C3_72B_DQ69
D26 RLD3_C3_72B_DQ70
C25 RLD3_C3_72B_DQ71
N24 RLD3_C3_72B_DM2
B25 RLD3_C3_72B_DM3
T26 RLD3_C3_72B_QK4_P
R26 RLD3_C3_72B_QK4_N
M27 RLD3_C3_72B_QK5_P
M28 RLD3_C3_72B_QK5_N
G26 RLD3_C3_72B_QK6_P
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Standard
Pin #
SSTL12 J10
SSTL12 K11
SSTL12 K13
SSTL12 L8
SSTL12 L10
SSTL12 L12
SSTL12 M9
SSTL12 M11
SSTL12 N8
SSTL12 D3
SSTL12 E4
SSTL12 C6
SSTL12 C4
SSTL12 C2
SSTL12 B5
SSTL12 B3
SSTL12 A6
SSTL12 A4
SSTL12 J4
SSTL12 K3
SSTL12 K1
SSTL12 L6
SSTL12 L4
SSTL12 L2
SSTL12 M5
SSTL12 M3
SSTL12 N6
SSTL12 B7
SSTL12 M7
DIFF_SSTL12 D9
DIFF_SSTL12 E8
DIFF_SSTL12 K9
DIFF_SSTL12 J8
DIFF_SSTL12 D5
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Chapter 3: Board Component Descriptions
Component Memory
Pin Name
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DM0
DM1
QK0
QK0_B
QK1
QK1_B
QK2
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Ref. Des.
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
U142
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