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set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Appendix B: Master Constraints File Listing
BE32
[get_ports "DDR4_C2_DM0"];
POD12_DCI
[get_ports "DDR4_C2_DM0"];
BB31
[get_ports "DDR4_C2_DM1"];
POD12_DCI
[get_ports "DDR4_C2_DM1"];
AV33
[get_ports "DDR4_C2_DM2"];
POD12_DCI
[get_ports "DDR4_C2_DM2"];
AR32
[get_ports "DDR4_C2_DM3"];
POD12_DCI
[get_ports "DDR4_C2_DM3"];
BC34
[get_ports "DDR4_C2_DM4"];
POD12_DCI
[get_ports "DDR4_C2_DM4"];
BE40
[get_ports "DDR4_C2_DM5"];
POD12_DCI
[get_ports "DDR4_C2_DM5"];
AY37
[get_ports "DDR4_C2_DM6"];
POD12_DCI
[get_ports "DDR4_C2_DM6"];
AV35
[get_ports "DDR4_C2_DM7"];
POD12_DCI
[get_ports "DDR4_C2_DM7"];
BE29
[get_ports "DDR4_C2_DM8"];
POD12_DCI
[get_ports "DDR4_C2_DM8"];
BA29
[get_ports "DDR4_C2_DM9"];
POD12_DCI
[get_ports "DDR4_C2_DM9"];
BF31
[get_ports "DDR4_C2_DQS0_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS0_C"];
BF30
[get_ports "DDR4_C2_DQS0_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS0_T"];
BA34
[get_ports "DDR4_C2_DQS1_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS1_C"];
AY34
[get_ports "DDR4_C2_DQS1_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS1_T"];
AV29
[get_ports "DDR4_C2_DQS2_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS2_C"];
AU29
[get_ports "DDR4_C2_DQS2_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS2_T"];
AP32
[get_ports "DDR4_C2_DQS3_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS3_C"];
AP31
[get_ports "DDR4_C2_DQS3_T"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS3_T"];
BF35
[get_ports "DDR4_C2_DQS4_C"];
DIFF_POD12_DCI
[get_ports "DDR4_C2_DQS4_C"];
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