Panasonic F77G User Manual page 276

Chapter 7 16-bit Timer
Count Timing of Synchronous TM7IO Input (Timer 7)
If the synchronous TM7IO input is selected, the synchronizing circuit output signal is input to the count
clock. The synchronizing circuit output signal is changed at the falling edge of the system clock after the
TM7IO input signal is changed. The binary counter counts up at the falling edge of the synchronizing
circuit output signal or the synchronizing circuit output signal that passed through the divide-by circuit.
TM7IO
input
System
clock (fs)
Synchronizing circuit
output (count clock)
TM7EN
flag
Compare
register 1
Binary
counter
Interrupt
request flag
Figure 7-4-2
When the synchronous TM7IO input is selected as the count clok source, the timer 7 counter
counts up in synchronization with the system clock. Therefore, the correct value is always
read. But, if the synchronous TM7IO is selected as the count clock source, CPU mode can-
not return from STOP/HALT mode.
VII - 16
16-bit Event Count
M
0000 0001
Count Timing of Synchronous TM7IO Input (Timer 7)
N
0002 N-1 N 0000