Panasonic F77G User Manual page 113

External Interrupt 2 Control Register (IRQ2ICR)
The external interrupt 2 control register (IRQ2ICR) controls interrupt level of external interrupt 2, active
edge, interrupt enable and interrupt request. Interrupt control register should be operated when the
maskable interrupt enable flag (MIE) of PSW is "0".
7 6
IRQ2 IRQ2
IRQ2ICR
LV1 LV0
Figure 3-2-4
5 4 3 2
- - -
REDG2
External Interrupt 2 Control Register (IRQ2ICR : x'03FE4', R/W)
1 0
(At reset : 0 0 0 - - - 0 0)
IRQ2IE IRQ2IR
IRQ2IR
0
1
IRQ2IE
0
1
REDG2
0
1
IRQ2
LV1
The CPU has interrupt levels from 0 to 3. These
flags set the interrupt level for interrupt requests.
Chapter 3 Interrupts
External interrupt request flag
No interrupt request
Interrupt request generated
External interrupt enable flag
Disable interrupt
Enable interrupt
External interrupt active edge flag
Falling edge
Rising edge
IRQ2
Interrupt level flag for external interrupt
LV0
Control Registers
III - 19