Panasonic F77G User Manual page 93

Oscillation Stabilization Wait Time Control Register
7 6
DLYCTR BUZOE BUZS2 BUZS1
Figure 2-8-4 Oscillation Stabilization Wait Time Control Register (DLYCTR : x'03F4D', R/W)
Control the Oscillation Stabilization Wait Time
At recovering from STOP mode, the bit 3-2 (DLYS1, DLYS0) of the oscillation stabilization wait time
control register can be set to select the oscillation stabilization wait time from 2
clock. The DLYCTR register is also used for controlling of buzzer functions.
At releasing from reset, the oscillation stabilization wait time is fixed to "2
is determined by the CPU mode control register (CPUM).
5 4 3 2
BUZS0 DLYS2 DLYS1 DLYS0
1 0
(At reset: 0 0 0 0 0 0 0 -)
-
DLYS2 DLYS1
0
1
Note : After reset is released, the oscillation stabilization
wait period is fixed at fs/2
BUZS2 BUZS1
0
1
BUZOE
0
1
[ Chapter 10 Buzzer ]
Chapter 2 CPU Basics
Oscillation stabilization wait
DLYS0
period selection
14
0 fs/2
0
12
1 fs/2
10
0 fs/2
1
8
1 fs/2
6
0 fs/2
0
4
1 fs/2
2
0 fs/2
1
Reserved
1
14
.
Buzzer output
BUZS0
frequency selection
14
0
fosc/2
0
13
1 fosc/2
12
fosc/2
0
1
11
1
fosc/2
10
0
fosc/2
0
9
1
fosc/2
4
0
fx/2
1
3
fx/2
1
P06 output selection
P06 port data output
P06 buzzer output
14 10 6
, 2 , 2 , 2
14 x system clock". System clock
Reset
2
x system
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