Panasonic F77G User Manual page 120

Chapter 3 Interrupts
Timer 6 Interrupt Control Register (TM6ICR)
The timer 6 interrupt control register (TM6ICR) controls interrupt level of timer 6 interrupt, interrupt
enable flag and interrupt request. Interrupt control register should be operated when the maskable inter-
rupt enable flag (MIE) of PSW is "0".
7 6
TM6 TM6
TM6ICR
LV1 LV0
Figure 3-2-14
III - 26
Control Registers
5 4 3 2
- - - -
Timer 6 Interrupt Control Register (TM6ICR : x'03FEF', R/W)
1 0
(At reset : 0 0 - - - - 0 0)
TM6IE TM6IR
TM6IR
0
1
TM6IE
0
1
TM6
LV1
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
Interrupt request flag
No interrupt request
Interrupt request generated
Interrupt enable flag
Disable interrupt
Enable interrupt
TM6
Interrupt level flag
LV0