Overview - Panasonic F77G User Manual

Chapter 2 CPU Basics
2-1

Overview

The MN101C CPU has a flexible optimized hardware configuration. It is a high speed CPU with a simple
and efficient instruction set. Specific features are as follows:
1. Minimized code sizes with instruction lengths based on 4-bit increments
The series keeps code sizes down by adopting a basic instruction length of one byte and variable
instruction lengths based on 4-bit increments.
2. Minimum execution instruction time is one system clock cycle.
3. Minimized register set that simplifies the architecture and supports C language
The instruction set has been determined, depending on the size and capacity of hardware, after
an analysis of embedded application programing code and creation code by C language compiler.
Therefore, the set is simple instruction using the minimal register set required for C language
compiler.
[
Structure
Instructions
Basic performance
Pipeline
Address space
External bus
Interrupt
Low-power
dissipation mode
II - 2
Overview
"MN101C LSI User's Manual" (Architecture Instructions) ]
Table 2-1-1 Basic Specifications
Load / store architecture
Six registers
Other
Number of instructions
Addressing modes
Instruction length
Instruction execution
Inter-register operation
Load / store
Conditional branch
3-stage (instruction fetch, decode, execution)
256 KB (max. 64 KB for data)
Address
Data
Minimum bus cycle
Vector interrupt
STOP mode
HALT mode
Data : 8-bit x 4
Address : 16-bit x 2
PC : 19-bit
PSW : 8-bit
SP : 16-bit
37
9
Basic portion : 1 byte (min.)
Extended portion : 0.5-byte x n
(0 n 9)
Min. 1 cycle
Min. 2 cycles
Min. 2 cycles
2 to 3 cycles
18-bit (max.)
8-bit
1 system clock cycle
3 interrupt levels