Panasonic F77G User Manual page 117

Timer 1 Interrupt Control Register (TM1ICR)
The timer 1 interrupt control register (TM1ICR) controls interrupt level of timer 1 interrupt, interrupt
enable flag and interrupt request. Interrupt control register should be operated when the maskable inter-
rupt enable flag (MIE) of PSW is "0".
7 6
TM1 TM1
TM1ICR
LV1 LV0
Figure 3-2-9
5 4 3 2
- - - -
Timer 1 Interrupt Control Register (TM1ICR : x'03FEA', R/W)
1 0
(At reset : 0 0 - - - - 0 0)
TM1IE TM1IR
TM1IR
0
1
TM1IE
0
1
TM1
LV1
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
Chapter 3 Interrupts
Interrupt request flag
No interrupt request
Interrupt request generated
Interrupt enable flag
Disable interrupt
Enable interrupt
TM1
Interrupt level flag
LV0
Control Registers
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