Panasonic F77G User Manual page 201

Port 6 Synchronous Output (External interrupt 2 IRQ2))
The synchronous output timing when the synchronous output event is set at the falling edge of the
external interrupt 2, is shown below. The latched data on port 6 is output in synchronization with the falling
edge of the IRQ2.
Port 6 output
X
latched data
External interrupt
(IRQ2)
Port 6 output X
Figure 4-11-2 Synchronous Output Timing by Event Generation (IRQ2)
Port 6 Synchronous Output (Timers 1,5 and 7)
The timer interrupt flag TMnIRQ is generated when binary counter and compare register are matched.
The latched data on port 6 is output from the port 6 in synchronization with the rising edge of the TMnIRQ.
About the setting of each timer operation, refer to chapter 6. 8-Bit timers, and chapter 7. 16-Bit timers.
Timer
count clock
Timer compare
register
Binary counter
N-1
Port 6 output
X
latched data
Interrupt request
flag
Port 6 output
Figure 4-11-3 Synchronous Output Timing by Event Generation (Timers 1, 5 and 7)
Y
Y
N 00 01 N-1
Y
X Y
X
Z
Z
N
N 00 01 N-1
X
Z
Z
Chapter 4 I/O Ports
Y
Y
N 00 01
Y
Y
Synchronous Output (Port 7)
N-1
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