Panasonic F77G User Manual page 448

Chapter 14 Automatic Transfer Controller
Data transfer
The basic ATC1 operation cycle is the "byte-data transfer cycle", in which ATC1 transfers a single byte
of data. This operation consists of two instruction cycles, a load and a store cycle. In the load cycle,
ATC1 reads the data from the source address of the source memory, and in the store cycle, ATC1
stores the read data to the destination address of the destination memory.
ATC1 transfers word-length data or a multi-byte stream of data by repeating the byte-data transfer
cycle as many times as necessary.
Transfer end
Once it has transferred all the data, ATC1 generates an interrupt (ATC1IRQ) and stop the automatic
transfer. In this way, the ATC1 block bypasses the software and automatically transfers data in a
continuous DMA operation.
In both the load and store cycles, the read and write access occurs to the memory exactly as
it does in a normal instruction execution. This means that the access timing is different de-
pending on the memory space. Also, the wait settings for I/O and external memory spaces
apply. The following is the access timing for each memory space, assuming no-wait situation.
The MCU core adds the CPU correction cycle (0.5 cycles) for the I/O space to correct the
internal clock when it accesses a peripheral for block. It sometimes adds it and sometimes
doesn't, depending on the internal state of the core.
In figure 14-3-1. ATC1 Timing Chart, the time, from the rising of DMA activation request signal
to the starting of LOAD cycle depends on the state of CPU, but it takes max. 8 cycles.
XIV - 10
Operation
- Internal ROM/RAM space
- External memory space
- I/O space (special registers)
2 cycles
2 cycles
3 cycles + CPU correction cycle (=0.5 cycles)