Panasonic F77G User Manual page 107

Chapter 3 Interrupts
Figure 3-1-7 shows the processing flow for multiple interrupts (interrupt 1: xxxLV1-xxxLV0='10', and
interrupt 2: xxxLV1-xxxLV0='00').
Main program
IM1,0='11'
Accepted because xxxLV1,0
Interrupt 1 generated <IM
(xxxLV1,0='10')
Interrupt acceptance cycle
IM1,0='10'
( )
Interrupt service routine: 1
* Interrupt 2 generated Accepted because xxxLV1,0
<IM
(xxxLV1,0='00')
Interrupt acceptance cycle
)
(
IM1,0='00'
Interrupt service routine: 2
Restart interrupt processing program 1
RTI ( )
IM1,0='10'
( )
RTI
IM1,0='11'
Parentheses ( ) indicate hardware processing
Figure 3-1-7 Processing Sequence with Multiple Interrupts Enabled
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