Special Function Registers List - Panasonic F77G User Manual

Chapter 17 Appendices
17-2

Special Function Registers List

Address Register
X'3F00' CPUM
X'3F01' MEMCTR
X'3F02' WDCTR
X'3F03' AREACTR
X'3F05' CSMD01
X'3F06' CSMD23
X'3F07' CSMD45
X'3F08' CSMD67
X'3F09' CSMD89
X'3F0A' SBNKR
X'3F0B' DBNKR
X'3F0E' RCCTR
X'3F10' P0OUT
X'3F11' P1OUT
X'3F12' P2OUT
X'3F15' P5OUT
X'3F16' P6OUT
X'3F17 P7OUT
X'3F18 P8OUT
XVII - 6
Special Function Registers List
Bit 7 Bit 6 Bit 5
SOSCDBL OSCSEL1 OSCSEL0
Clock Switching
IOW1 IOW0 IVBM
I/O Wait Setup
Interrupt Vector
Address
- - WDTC2
The lowest value for clear Setup
CS8EXT CS7EXT CS6EXT
CS1MD CS1W2 CS1W1
Bus mode Wait mode selection
selection
CS3MD CS3W2 CS3W1
Bus mode Wait mode selection
selection
CS5MD CS5W2 CS5W1
Bus mode Wait mode selection
selection
CS7MD CS7W2 CS7W1
Bus mode Wait mode selection
selection
Reserved CS9W2 CS9W1
Set always Wait mode selection
to "1"
- - -
- - -
- - -
- P0OUT6 P0OUT5
- - -
- -
P2OUT7
Port 2
Output Data
- - -
P6OUT7 P6OUT6 P6OUT5
P7OUT7 P7OUT6 P7OUT5
P8OUT7 P8OUT6 P8OUT5
Bit Symbol / Initial Value / Description
Bit 4 Bit 3
OSCDBL STOP
STOP mode
Setup
EXMEM EXWH
Switch Switch
Memory Wait
WDTC1 WDTC0
CS5EXT CS4EXT
Internal ROM/External Memory Switching
CS1W0 -
CS3W0 CS2MD
Bus mode
selection
CS5W0 CS4MD
Bus mode
selection
CS7W0 CS6MD
Bus mode
selection
CS9W0 CS8MD
Bus mode
selection
- -
- -
- -
P0OUT4 P0OUT3
Port 0 Output Data
P1OUT4 P1OUT3
Port 1 Output Data
P2OUT4 P2OUT3
Port 2 Output Data
P5OUT4 P5OUT3
Port 5 Output Data
P6OUT4 P6OUT3
Port 6 Output Data
P7OUT4 P7OUT3
Port 7 Output Data
P8OUT4 P8OUT3
Port 8 Output Data
Bit 2 Bit 1 Bit 0
HALT OSC1 OSC0
HALT Mode Oscillation Control
Setup
IRWE EXW1 EXW0
Fixed Wait Setup
Software Wri t es
Setup
WDTS1 WDTS0 WDEN
Watchdog Time-out WDT
Period Setup Activation
CS3EXT CS2EXT CS1EXT
CS0W2 CS0W1 CS0W0
Wait mode selection
CS2W2 CS2W1 CS2W0
Wait mode selection
CS4W2 CS4W1 CS4W0
Wait mode selection
CS6W2 CS6W1 CS6W0
Wait mode selection
CS8W2 CS8W1 CS8W0
Wait mode selection
- SBA1 SBA0
Bank for Source
Address Setup
- DBA1 DBA0
Bank for Destination
Address Setup
RC2EN RC1EN RC0EN
ROM Correction Control
P0OUT2 P0OUT1 P0OUT0
P1OUT2 P1OUT1 P1OUT0
P2OUT2 P2OUT1 P2OUT0
P5OUT2 P5OUT1 P5OUT0
P6OUT2 P6OUT1 P6OUT0
P7OUT2 P7OUT1 P7OUT0
P8OUT2 P8OUT1 P8OUT0
Page
II - 21
II - 25
II - 16
IX - 3
II - 17
II - 18
II - 18
II -18
II - 18
II - 18
II - 28
II - 28
II - 32
IV - 7
IV - 13
IV - 18
IV - 22
IV - 27
IV - 31
IV - 38