Panasonic F77G User Manual page 124

Chapter 3 Interrupts
Serial Interface 0 Reception Interrupt Control Register (SC0RICR)
The serial Interface 0 reception interrupt control register (SC0RICR) controls interrupt level of serial
Interface 0 reception interrupt, interrupt enable flag and interrupt request. Interrupt control register
should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
7
SC0R SC0R
SC0RICR
LV1
Figure 3-2-18
III - 30
Control Registers
6 5 4 3
- - -
LV0
Serial Interface 0 Reception Interrupt Control register
(SC0RICR:x'03FF4', R/W)
2 1 0
-
SC0RIE SC0RIR
SC0R
LV1
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
(at reset : 0 0 - - - - 0 0 )
Serial interface 0 reception
SC0RIR
interrupt request flag
0 No interrupt request flag
1 Interrupt request generated
Serial interface 0 reception
SC0RIE
interrupt enable flag
0 Disable interrupt
1 Enable interrupt
Serial interface 0 reception
SC0R
interrupt level flag
LV0